{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,13]],"date-time":"2026-04-13T17:59:34Z","timestamp":1776103174569,"version":"3.50.1"},"reference-count":45,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2020,8,26]],"date-time":"2020-08-26T00:00:00Z","timestamp":1598400000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"NSF","award":["CNS-1564014, CCF 1514269"],"award-info":[{"award-number":["CNS-1564014, CCF 1514269"]}]},{"name":"ARO","award":["W911NF-17-1-0485"],"award-info":[{"award-number":["W911NF-17-1-0485"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2020,10,31]]},"abstract":"<jats:p>3D Network-on-Chip (3D NoC) enables design of high-performance and energy-efficient manycore computing platforms. Two of the commonly used vertical interconnection technologies are: through silicon via (TSV) and near-field inductive coupling (NFIC). Both TSV- and NFIC-based links introduce additional area overhead. One of the possible ways to reduce the area overhead is to design partially connected 3D NoC with minimal effect on overall performance. The achievable performance of the partially connected 3D NoCs depends on the area, energy, and bandwidth of the vertical links. Moreover, the electromigration-induced failure of TSV is more severe than the misalignment-induced error in NFIC. By considering all these pertinent factors, we demonstrate that it is indeed possible to design a partially connected NFIC-based 3D NoC that performs as good as a fully connected TSV-based counterpart when the data rate is below a certain limit. For higher data rates, the partially connected TSV-based 3D NoC is a viable solution. However, NFIC-based 3D NoC is always more robust than the TSV-based counterpart.<\/jats:p>","DOI":"10.1145\/3394919","type":"journal-article","created":{"date-parts":[[2020,7,7]],"date-time":"2020-07-07T12:38:34Z","timestamp":1594125514000},"page":"1-17","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Making a Case for Partially Connected 3D NoC"],"prefix":"10.1145","volume":"16","author":[{"given":"Aqeeb Iqbal","family":"Arka","sequence":"first","affiliation":[{"name":"Washington State University, Pullman, WA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Srinivasan","family":"Gopal","sequence":"additional","affiliation":[{"name":"Intel Corporation, Hillsboro, OR"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Janardhan Rao","family":"Doppa","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Deukhyoun","family":"Heo","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Partha Pratim","family":"Pande","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,8,26]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the IEEE Hot Chips Symposium. DOI:https:\/\/doi.org\/10","author":"Ditzel D.","year":"2014","unstructured":"D. Ditzel , T. Kuroda , and S. Lee . 2014. Low-cost 3D chip stacking with ThruChip wireless connections . In Proceedings of the IEEE Hot Chips Symposium. DOI:https:\/\/doi.org\/10 .1109\/HOTCHIPS. 2014 .7478813 D. Ditzel, T. Kuroda, and S. Lee. 2014. Low-cost 3D chip stacking with ThruChip wireless connections. In Proceedings of the IEEE Hot Chips Symposium. DOI:https:\/\/doi.org\/10.1109\/HOTCHIPS.2014.7478813"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the IEEE International Solid-state Circuits Conference.","author":"Kuroda T.","year":"2014","unstructured":"T. Kuroda . 2014 . 3D Integration, power delivery, and contactless interconnect by near field coupling . In Proceedings of the IEEE International Solid-state Circuits Conference. T. Kuroda. 2014. 3D Integration, power delivery, and contactless interconnect by near field coupling. In Proceedings of the IEEE International Solid-state Circuits Conference."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2011.5784499"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2498550"},{"key":"e_1_2_1_5_1","volume-title":"Proceedings of the IEEE Custom Integrated Circuits Conference. 571--574","author":"Lu Y. R.","year":"2006","unstructured":"Y. R. Lu , Y. Lee , W. J. McMahon , and T. Fung . 2006. Robust inductor design for RF circuits . In Proceedings of the IEEE Custom Integrated Circuits Conference. 571--574 . DOI:https:\/\/doi.org\/10.1109\/CICC. 2006 .320993 Y. R. Lu, Y. Lee, W. J. McMahon, and T. Fung. 2006. Robust inductor design for RF circuits. In Proceedings of the IEEE Custom Integrated Circuits Conference. 571--574. DOI:https:\/\/doi.org\/10.1109\/CICC.2006.320993"},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the Symposium on VLSI Technology. C22--C23","author":"Dutoit D.","year":"2013","unstructured":"D. Dutoit 2013 . A 0.9 pJ\/bit, 12.8 GByte\/s WideIO memory interface in a 3D-IC NoC-based MPSoC . In Proceedings of the Symposium on VLSI Technology. C22--C23 . D. Dutoit et al. 2013. A 0.9 pJ\/bit, 12.8 GByte\/s WideIO memory interface in a 3D-IC NoC-based MPSoC. In Proceedings of the Symposium on VLSI Technology. C22--C23."},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-aided Design (ICCAD\u201915)","author":"Das S.","year":"2015","unstructured":"S. Das , J. R. Doppa , D. H. Kim , P. P. Pande , and K. Chakrabarty . 2015. Optimizing 3D NoC Ddesign for energy efficiency: A machine learning approach . In Proceedings of the IEEE\/ACM International Conference on Computer-aided Design (ICCAD\u201915) . IEEE Press, 705--712. DOI:https:\/\/doi.org\/10.1109\/ICCAD. 2015 .7372639 S. Das, J. R. Doppa, D. H. Kim, P. P. Pande, and K. Chakrabarty. 2015. Optimizing 3D NoC Ddesign for energy efficiency: A machine learning approach. In Proceedings of the IEEE\/ACM International Conference on Computer-aided Design (ICCAD\u201915). IEEE Press, 705--712. DOI:https:\/\/doi.org\/10.1109\/ICCAD.2015.7372639"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2017.12.002"},{"key":"e_1_2_1_9_1","volume-title":"Proceedings of the 18th International Symposium on Quality Electronic Design (ISQED\u201917)","author":"Lee D.","year":"2017","unstructured":"D. Lee , S. Das , and P. P. Pande . 2017. Performance-thermal trade-offs for a VFI-enabled 3D NoC architecture . In Proceedings of the 18th International Symposium on Quality Electronic Design (ISQED\u201917) . 271--276. DOI:https:\/\/doi.org\/10.1109\/ISQED. 2017 .7918327 D. Lee, S. Das, and P. P. Pande. 2017. Performance-thermal trade-offs for a VFI-enabled 3D NoC architecture. In Proceedings of the 18th International Symposium on Quality Electronic Design (ISQED\u201917). 271--276. DOI:https:\/\/doi.org\/10.1109\/ISQED.2017.7918327"},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-aided Design (ICCAD\u201911)","author":"Pathak M.","year":"2011","unstructured":"M. Pathak , J. Pak , D. Z. Pan , and S. K. Lim . 2011. Electromigration modeling, and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs . In Proceedings of the IEEE\/ACM International Conference on Computer-aided Design (ICCAD\u201911) . 555--562. DOI:https:\/\/doi.org\/10.1109\/ICCAD. 2011 .6105385 M. Pathak, J. Pak, D. Z. Pan, and S. K. Lim. 2011. Electromigration modeling, and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs. In Proceedings of the IEEE\/ACM International Conference on Computer-aided Design (ICCAD\u201911). 555--562. DOI:https:\/\/doi.org\/10.1109\/ICCAD.2011.6105385"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.3043798"},{"key":"e_1_2_1_12_1","volume-title":"Proceedings of the Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201916)","author":"Das S.","unstructured":"S. Das , J. R. Doppa , P. P. Pande , and K. Chakrabarty . 2016. Reliability, and performance trade-offs for 3D NoC-enabled multicore chips . In Proceedings of the Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201916) . 1429--1432. S. Das, J. R. Doppa, P. P. Pande, and K. Chakrabarty. 2016. Reliability, and performance trade-offs for 3D NoC-enabled multicore chips. In Proceedings of the Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201916). 1429--1432."},{"key":"e_1_2_1_13_1","volume-title":"Proceedings of the Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201917)","author":"Das S.","year":"2017","unstructured":"S. Das , J. R. Doppa , P. P. Pande , and K. Chakrabarty . 2017b. Robust TSV-based 3D NoC design to counteract electromigration, and crosstalk noise . In Proceedings of the Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201917) . 1366--1371. DOI:https:\/\/doi.org\/10.23919\/DATE. 2017 .7927205 S. Das, J. R. Doppa, P. P. Pande, and K. Chakrabarty. 2017b. Robust TSV-based 3D NoC design to counteract electromigration, and crosstalk noise. In Proceedings of the Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201917). 1366--1371. DOI:https:\/\/doi.org\/10.23919\/DATE.2017.7927205"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2604288"},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the IEEE International Solid-state Circuits Conference. 448--614","author":"Gu Q.","year":"2007","unstructured":"Q. Gu , Z. Xu , J. Ko , and M. F. Chang . 2007. Two 10Gb\/s\/pin low-power interconnect methods for 3D ICs . In Proceedings of the IEEE International Solid-state Circuits Conference. 448--614 . DOI:https:\/\/doi.org\/10.1109\/ISSCC. 2007 .373487 Q. Gu, Z. Xu, J. Ko, and M. F. Chang. 2007. Two 10Gb\/s\/pin low-power interconnect methods for 3D ICs. In Proceedings of the IEEE International Solid-state Circuits Conference. 448--614. DOI:https:\/\/doi.org\/10.1109\/ISSCC.2007.373487"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.249"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2440317"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2010.5703378"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2865704"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164023"},{"key":"e_1_2_1_21_1","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-aided Design (ICCAD\u201917)","author":"Das S.","year":"2017","unstructured":"S. Das , S. Gopal , D. Heo , and P. P. Pande . 2017. Energy-efficient and robust 3D NoCs with contactless vertical links . In Proceedings of the IEEE\/ACM International Conference on Computer-aided Design (ICCAD\u201917) . 1--6. DOI:https:\/\/doi.org\/10.1109\/ICCAD. 2017 .8501894 S. Das, S. Gopal, D. Heo, and P. P. Pande. 2017. Energy-efficient and robust 3D NoCs with contactless vertical links. In Proceedings of the IEEE\/ACM International Conference on Computer-aided Design (ICCAD\u201917). 1--6. DOI:https:\/\/doi.org\/10.1109\/ICCAD.2017.8501894"},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the 11th IEEE\/ACM International Symposium on Networks-on-Chip (NOCS\u201917)","author":"Gopal S.","unstructured":"S. Gopal , S. Das , D. Heo , and P. P. Pande . 2017. Energy and area-efficient near field inductive coupling: A case study on 3D NoC . In Proceedings of the 11th IEEE\/ACM International Symposium on Networks-on-Chip (NOCS\u201917) . Association for Computing Machinery, New York, NY. 1--8. DOI:https:\/\/doi.org\/10.1145\/3130218.3130224 S. Gopal, S. Das, D. Heo, and P. P. Pande. 2017. Energy and area-efficient near field inductive coupling: A case study on 3D NoC. In Proceedings of the 11th IEEE\/ACM International Symposium on Networks-on-Chip (NOCS\u201917). Association for Computing Machinery, New York, NY. 1--8. DOI:https:\/\/doi.org\/10.1145\/3130218.3130224"},{"key":"e_1_2_1_23_1","volume-title":"Proceedings of the Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201914)","author":"Matsutani H.","year":"2014","unstructured":"H. Matsutani , M. Koibuchi , I. Fujiwara , T. Kagami , Y. Take , T. Kuroda , P. Bogdan , R. Marculescu , and H. Amano . 2014. Low-latency wireless 3D NoCs via randomized shortcut chips . In Proceedings of the Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201914) . 1--6. DOI:https:\/\/doi.org\/10.7873\/DATE. 2014 .286 H. Matsutani, M. Koibuchi, I. Fujiwara, T. Kagami, Y. Take, T. Kuroda, P. Bogdan, R. Marculescu, and H. Amano. 2014. Low-latency wireless 3D NoCs via randomized shortcut chips. In Proceedings of the Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201914). 1--6. DOI:https:\/\/doi.org\/10.7873\/DATE.2014.286"},{"key":"e_1_2_1_24_1","volume-title":"Proceedings of the 56th Annual Design Automation Conference (DAC\u201919)","author":"Koibuchi M.","unstructured":"M. Koibuchi , L. Leong , T. Totoki , N. Niwa , H. Matsutani , H. Amano , and H. Casanova . 2019. Sparse 3-D NoCs with inductive coupling . In Proceedings of the 56th Annual Design Automation Conference (DAC\u201919) . Association for Computing Machinery, New York, NY. 1--6. DOI:https:\/\/doi.org\/10.1145\/3316781.3317913 M. Koibuchi, L. Leong, T. Totoki, N. Niwa, H. Matsutani, H. Amano, and H. Casanova. 2019. Sparse 3-D NoCs with inductive coupling. In Proceedings of the 56th Annual Design Automation Conference (DAC\u201919). Association for Computing Machinery, New York, NY. 1--6. DOI:https:\/\/doi.org\/10.1145\/3316781.3317913"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.239"},{"key":"e_1_2_1_26_1","volume-title":"Proceedings of the 25th Great Lakes Symposium on VLSI (GLSVLSI\u201915)","author":"Das S.","year":"2060","unstructured":"S. Das , D. Lee , D. H. Kim , and P. P. Pande . 2015. Small-world network enabled energy-efficient and robust 3D NoC architectures . In Proceedings of the 25th Great Lakes Symposium on VLSI (GLSVLSI\u201915) . Association for Computing Machinery, New York, NY. 133--138. DOI:https:\/\/doi.org\/10.1145\/274 2060 .2742085 S. Das, D. Lee, D. H. Kim, and P. P. Pande. 2015. Small-world network enabled energy-efficient and robust 3D NoC architectures. In Proceedings of the 25th Great Lakes Symposium on VLSI (GLSVLSI\u201915). Association for Computing Machinery, New York, NY. 133--138. DOI:https:\/\/doi.org\/10.1145\/2742060.2742085"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2786572.2786592"},{"key":"e_1_2_1_28_1","volume-title":"Proceedings of the 9th International Symposium on Networks-on-Chip (NOCS\u201915)","author":"Xue Y.","unstructured":"Y. Xue and P. Bogdan . 2015. User cooperation network coding approach for NoC performance improvement . In Proceedings of the 9th International Symposium on Networks-on-Chip (NOCS\u201915) . Association for Computing Machinery, New York, NY. 1--8. DOI:https:\/\/doi.org\/10.1145\/2786572.2786575 Y. Xue and P. Bogdan. 2015. User cooperation network coding approach for NoC performance improvement. In Proceedings of the 9th International Symposium on Networks-on-Chip (NOCS\u201915). Association for Computing Machinery, New York, NY. 1--8. DOI:https:\/\/doi.org\/10.1145\/2786572.2786575"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2612647"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034431"},{"key":"e_1_2_1_31_1","volume-title":"Proceedings of the IEEE Custom Integrated Circuits Conference. 449--452","author":"Saito M.","year":"2009","unstructured":"M. Saito , Y. Sugimori , Y. Kohama , Y. Yoshida , N. Miura , H. Ishikuro , and T. Kuroda . 2009. 47% power reduction and 91% area reduction in inductive-coupling programmable bus for N, and flash memory stacking . In Proceedings of the IEEE Custom Integrated Circuits Conference. 449--452 . DOI:https:\/\/doi.org\/10.1109\/CICC. 2009 .5280819 M. Saito, Y. Sugimori, Y. Kohama, Y. Yoshida, N. Miura, H. Ishikuro, and T. Kuroda. 2009. 47% power reduction and 91% area reduction in inductive-coupling programmable bus for N, and flash memory stacking. In Proceedings of the IEEE Custom Integrated Circuits Conference. 449--452. DOI:https:\/\/doi.org\/10.1109\/CICC.2009.5280819"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2012.2189212"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2015.7334599"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2074070"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878263"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2889053"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.142"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2512611"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2007.900837"},{"key":"e_1_2_1_41_1","volume-title":"Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software. 33--42","author":"Agarwal N.","year":"2009","unstructured":"N. Agarwal , T. Krishna , L. Peh , and N. Jha . 2009. GARNET: A detailed on-chip network model inside a full-system simulator . In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software. 33--42 . DOI:https:\/\/doi.org\/10.1109\/ISPASS. 2009 .4919636 N. Agarwal, T. Krishna, L. Peh, and N. Jha. 2009. GARNET: A detailed on-chip network model inside a full-system simulator. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software. 33--42. DOI:https:\/\/doi.org\/10.1109\/ISPASS.2009.4919636"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2006.12"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1995.524546"},{"key":"e_1_2_1_44_1","unstructured":"Christian Bienia. 2011.\n  Benchmarking modern multiprocessors\n  . Ph.D. Dissertation. \n  Princeton University NJ.  Christian Bienia. 2011. Benchmarking modern multiprocessors. Ph.D. Dissertation. Princeton University NJ."},{"key":"e_1_2_1_45_1","volume-title":"Proceedings of the IEEE International Solid-state Circuits Conference. 142--144","author":"Liu Y.","year":"2012","unstructured":"Y. Liu , W. Luk , and D. Friedman . 2012. A compact low-power 3D I\/O in 45nm CMOS . In Proceedings of the IEEE International Solid-state Circuits Conference. 142--144 . DOI:https:\/\/doi.org\/10.1109\/ISSCC. 2012 .6176900 Y. Liu, W. Luk, and D. Friedman. 2012. A compact low-power 3D I\/O in 45nm CMOS. In Proceedings of the IEEE International Solid-state Circuits Conference. 142--144. DOI:https:\/\/doi.org\/10.1109\/ISSCC.2012.6176900"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3394919","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3394919","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3394919","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:48:00Z","timestamp":1750193280000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3394919"}},"subtitle":["NFIC versus TSV"],"short-title":[],"issued":{"date-parts":[[2020,8,26]]},"references-count":45,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2020,10,31]]}},"alternative-id":["10.1145\/3394919"],"URL":"https:\/\/doi.org\/10.1145\/3394919","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"value":"1550-4832","type":"print"},{"value":"1550-4840","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,8,26]]},"assertion":[{"value":"2020-01-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-08-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}