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Syst."],"published-print":{"date-parts":[[2020,9,30]]},"abstract":"<jats:p>Wireless communication standards such as Long-term Evolution (LTE) are rapidly changing to support the high data-rate of wireless devices. The physical layer baseband processing has strict real-time deadlines, especially in the next-generation applications enabled by the 5G standard. Existing basestation transceivers utilize customized DSP cores or fixed-function hardware accelerators for physical layer baseband processing. However, these approaches incur significant non-recurring engineering costs and are inflexible to newer standards or updates. Software-programmable processors offer more adaptability. However, it is challenging to sustain guaranteed worst-case latency and throughput at reasonably low-power on shared-memory many-core architectures featuring inherently unpredictable design choices, such as caches and Network-on-chip (NoC).<\/jats:p>\n          <jats:p>\n            We propose\n            <jats:italic>SPECTRUM<\/jats:italic>\n            , a predictable, software-defined many-core architecture that exploits the massive parallelism of the LTE\/5G baseband processing workload. The focus is on designing scalable lightweight hardware that can be programmed and defined by sophisticated software mechanisms.\n            <jats:italic>SPECTRUM<\/jats:italic>\n            employs hundreds of lightweight in-order cores augmented with custom instructions that provide predictable timing, a purely software-scheduled NoC that orchestrates the communication to avoid any contention, and per-core software-controlled scratchpad memory with deterministic access latency. Compared to many-core architecture like Skylake-SP (average power 215 W) that drops 14% packets at high-traffic load, 256-core\n            <jats:italic>SPECTRUM<\/jats:italic>\n            by definition has zero packet drop rate at significantly lower average power of 24 W.\n            <jats:italic>SPECTRUM<\/jats:italic>\n            consumes 2.11\u00d7 lower power than C66x DSP cores+accelerator platform in baseband processing. We also enable\n            <jats:italic>SPECTRUM<\/jats:italic>\n            to handle dynamic workloads with multiple service categories present in 5G mobile network (Enhanced Mobile Broadband (eMBB), Ultra-reliable and Low-latency Communications (URLLC), and Massive Machine Type Communications (mMTC)), using a run-time scheduling and mapping algorithm. Experimental evaluations show that our algorithm performs task\/NoC mapping at run-time on fewer cores compared to the static mapping (that reserves cores exclusively for each service category) while still meeting the differentiated latency and reliability requirements.\n          <\/jats:p>","DOI":"10.1145\/3400032","type":"journal-article","created":{"date-parts":[[2020,9,26]],"date-time":"2020-09-26T10:15:05Z","timestamp":1601115305000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["SPECTRUM"],"prefix":"10.1145","volume":"19","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0259-6456","authenticated-orcid":false,"given":"Vanchinathan","family":"Venkataramani","sequence":"first","affiliation":[{"name":"National University of Singapore, Singapore"}]},{"given":"Aditi","family":"Kulkarni","sequence":"additional","affiliation":[{"name":"National University of Singapore, Singapore"}]},{"given":"Tulika","family":"Mitra","sequence":"additional","affiliation":[{"name":"National University of Singapore, Singapore"}]},{"given":"Li-Shiuan","family":"Peh","sequence":"additional","affiliation":[{"name":"National University of Singapore, Singapore"}]}],"member":"320","published-online":{"date-parts":[[2020,9,26]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"2009. 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