{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,14]],"date-time":"2026-04-14T16:21:09Z","timestamp":1776183669820,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,11,2]],"date-time":"2020-11-02T00:00:00Z","timestamp":1604275200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,11,2]]},"DOI":"10.1145\/3400302.3415624","type":"proceedings-article","created":{"date-parts":[[2020,12,18]],"date-time":"2020-12-18T01:16:38Z","timestamp":1608254198000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":46,"title":["A customized graph neural network model for guiding analog IC placement"],"prefix":"10.1145","author":[{"given":"Yaguang","family":"Li","sequence":"first","affiliation":[{"name":"Texas A&M University"}]},{"given":"Yishuang","family":"Lin","sequence":"additional","affiliation":[{"name":"Texas A&M University"}]},{"given":"Meghna","family":"Madhusudan","sequence":"additional","affiliation":[{"name":"University of Minnesota"}]},{"given":"Arvind","family":"Sharma","sequence":"additional","affiliation":[{"name":"University of Minnesota"}]},{"given":"Wenbin","family":"Xu","sequence":"additional","affiliation":[{"name":"Texas A&M University"}]},{"given":"Sachin S.","family":"Sapatnekar","sequence":"additional","affiliation":[{"name":"University of Minnesota"}]},{"given":"Ramesh","family":"Harjani","sequence":"additional","affiliation":[{"name":"University of Minnesota"}]},{"given":"Jiang","family":"Hu","sequence":"additional","affiliation":[{"name":"Texas A&M University"}]}],"member":"320","published-online":{"date-parts":[[2020,12,17]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.205002"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.391116"},{"issue":"7","key":"e_1_3_2_1_3_1","first-page":"721","article-title":"Symmetry within the sequence-pair representation in the context of placement for analog design","volume":"19","author":"Balasa F.","year":"2000","unstructured":"F. Balasa and K. Lampaert , \" Symmetry within the sequence-pair representation in the context of placement for analog design ,\" IEEE TCAD , vol. 19 , no. 7 , pp. 721 -- 731 , 2000 . F. Balasa and K. Lampaert, \"Symmetry within the sequence-pair representation in the context of placement for analog design,\" IEEE TCAD, vol. 19, no. 7, pp. 721--731, 2000.","journal-title":"IEEE TCAD"},{"key":"e_1_3_2_1_4_1","volume-title":"ICCAD","author":"Strasser M.","year":"2008","unstructured":"M. Strasser , M. Eick , H. Grab , U. Schlichtmann , and F. M. Johannes , \" Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions,\" in Proc . ICCAD , 2008 . M. Strasser, M. Eick, H. Grab, U. Schlichtmann, and F. M. Johannes, \"Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions,\" in Proc. ICCAD, 2008."},{"issue":"6","key":"e_1_3_2_1_5_1","first-page":"791","article-title":"Analog placement based on symmetry-island formulation","volume":"28","author":"Lin P.-H.","year":"2009","unstructured":"P.-H. Lin , Y.-W. Chang , and S.-C. Lin , \" Analog placement based on symmetry-island formulation ,\" IEEE TCAD , vol. 28 , no. 6 , pp. 791 -- 804 , 2009 . P.-H. Lin, Y.-W. Chang, and S.-C. Lin, \"Analog placement based on symmetry-island formulation,\" IEEE TCAD, vol. 28, no. 6, pp. 791--804, 2009.","journal-title":"IEEE TCAD"},{"key":"e_1_3_2_1_6_1","first-page":"292","volume-title":"DAC","author":"Lin C.-W.","year":"2010","unstructured":"C.-W. Lin , J.-M. Lin , C.-P. Huang , and S.-J. Chang , \"Performance-driven analog placement considering boundary constraint,\" in Proc . DAC , 2010 , pp. 292 -- 297 . C.-W. Lin, J.-M. Lin, C.-P. Huang, and S.-J. Chang, \"Performance-driven analog placement considering boundary constraint,\" in Proc. DAC, 2010, pp. 292--297."},{"issue":"1","key":"e_1_3_2_1_7_1","first-page":"85","article-title":"Simultaneous handling of symmetry, common centroid, and general placement constraints","volume":"30","author":"Ma Q.","year":"2010","unstructured":"Q. Ma , L. Xiao , Y.-C. Tam , and E. F. Young , \" Simultaneous handling of symmetry, common centroid, and general placement constraints ,\" IEEE TCAD , vol. 30 , no. 1 , pp. 85 -- 95 , 2010 . Q. Ma, L. Xiao, Y.-C. Tam, and E. F. Young, \"Simultaneous handling of symmetry, common centroid, and general placement constraints,\" IEEE TCAD, vol. 30, no. 1, pp. 85--95, 2010.","journal-title":"IEEE TCAD"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429516"},{"key":"e_1_3_2_1_9_1","first-page":"1","volume-title":"DAC","author":"Ou H. C.","year":"2015","unstructured":"H. C. Ou , K. H. Tseng , J. Y. Liu , I. P. Wu , and Y. W. Chang , \" Layout-dependent-effects-aware analytical analog placement,\" in Proc . DAC , 2015 , pp. 1 -- 6 . H. C. Ou, K. H. Tseng, J. Y. Liu, I. P. Wu, and Y. W. Chang, \"Layout-dependent-effects-aware analytical analog placement,\" in Proc. DAC, 2015, pp. 1--6."},{"key":"e_1_3_2_1_10_1","first-page":"1","volume-title":"Analog layout synthesis with knowledge mining,\" in European Conference on Circuit Theory and Design (ECCTD)","author":"Wu P.-H.","year":"2015","unstructured":"P.-H. Wu , P. H. Lin , and T. Y. Ho , \" Analog layout synthesis with knowledge mining,\" in European Conference on Circuit Theory and Design (ECCTD) , 2015 , pp. 1 -- 4 . P.-H. Wu, P. H. Lin, and T. Y. Ho, \"Analog layout synthesis with knowledge mining,\" in European Conference on Circuit Theory and Design (ECCTD), 2015, pp. 1--4."},{"key":"e_1_3_2_1_11_1","first-page":"617","volume-title":"ASPDAC","author":"Lin P. H.","year":"2016","unstructured":"P. H. Lin , Y. W. Chang , and C. M. Hung , \" Recent research development and new challenges in analog layout synthesis,\" in Proc . ASPDAC , 2016 , pp. 617 -- 622 . P. H. Lin, Y. W. Chang, and C. M. Hung, \"Recent research development and new challenges in analog layout synthesis,\" in Proc. ASPDAC, 2016, pp. 617--622."},{"key":"e_1_3_2_1_12_1","first-page":"55","volume-title":"ISPD","author":"Xu B.","year":"2017","unstructured":"B. Xu , S. Li , X. Xu , N. Sun , and D. Z. Pan , \" Hierarchical and analytical placement techniques for high-performance analog circuits,\" in Proc . ISPD , 2017 , pp. 55 -- 62 . B. Xu, S. Li, X. Xu, N. Sun, and D. Z. Pan, \"Hierarchical and analytical placement techniques for high-performance analog circuits,\" in Proc. ISPD, 2017, pp. 55--62."},{"key":"e_1_3_2_1_13_1","first-page":"19","volume-title":"ISPD","author":"Xu B.","year":"2019","unstructured":"B. Xu , S. Li , C.-W. Pui , D. Liu , L. Shen , Y. Lin , N. Sun , and D. Z. Pan , \" Device layer-aware analytical placement for analog circuits,\" in Proc . ISPD , 2019 , pp. 19 -- 26 . B. Xu, S. Li, C.-W. Pui, D. Liu, L. Shen, Y. Lin, N. Sun, and D. Z. Pan, \"Device layer-aware analytical placement for analog circuits,\" in Proc. ISPD, 2019, pp. 19--26."},{"key":"e_1_3_2_1_14_1","first-page":"293","volume-title":"ASPDAC","author":"Liu Z.","year":"2010","unstructured":"Z. Liu and L. Zhang , \" A performance-constrained template-based layout retargeting algorithm for analog integrated circuits,\" in Proc . ASPDAC , 2010 , pp. 293 -- 298 . Z. Liu and L. Zhang, \"A performance-constrained template-based layout retargeting algorithm for analog integrated circuits,\" in Proc. ASPDAC, 2010, pp. 293--298."},{"key":"e_1_3_2_1_15_1","first-page":"7364","volume-title":"ICML","author":"Zhang G.","year":"2019","unstructured":"G. Zhang , H. He , and D. Katabi , \" Circuit-GNN: Graph neural networks for distributed circuit design,\" in Proc . ICML , 2019 , pp. 7364 -- 7373 . G. Zhang, H. He, and D. Katabi, \"Circuit-GNN: Graph neural networks for distributed circuit design,\" in Proc. ICML, 2019, pp. 7364--7373."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317930"},{"key":"e_1_3_2_1_17_1","first-page":"1","volume-title":"ICCAD","author":"Zhu K.","year":"2019","unstructured":"K. Zhu , M. Liu , Y. Lin , B. Xu , S. Li , X. Tang , N. Sun , and D. Z. Pan , \" Genius route: A new analog routing paradigm using generative neural network guidance,\" in Proc . ICCAD , 2019 , pp. 1 -- 8 . K. Zhu, M. Liu, Y. Lin, B. Xu, S. Li, X. Tang, N. Sun, and D. Z. Pan, \"Genius route: A new analog routing paradigm using generative neural network guidance,\" in Proc. ICCAD, 2019, pp. 1--8."},{"key":"e_1_3_2_1_18_1","volume-title":"DATE","author":"Kunal K.","year":"2020","unstructured":"K. Kunal , T. Dhar , M. Madhusudan , J. Poojary , A. Sharma , W. Xu , S. M. Burns , J. Hu , R. Harjani , and S. S. Sapatnekar , \" GANA: Graph convolutional network based automated netlist annotation for analog circuits,\" in Proc . DATE , 2020 . K. Kunal, T. Dhar, M. Madhusudan, J. Poojary, A. Sharma, W. Xu, S. M. Burns, J. Hu, R. Harjani, and S. S. Sapatnekar, \"GANA: Graph convolutional network based automated netlist annotation for analog circuits,\" in Proc. DATE, 2020."},{"key":"e_1_3_2_1_19_1","first-page":"1","article-title":"Towards decrypting the art of analog layout, placement quality prediction via transfer learning","author":"Liu M.","year":"2020","unstructured":"M. Liu , K. Zhu , J. Gu , L. Shen , X. Tang , N. Sun , and D. Z. Pan , \" Towards decrypting the art of analog layout, placement quality prediction via transfer learning ,\" in Proc. DATE , 2020 , pp. 1 -- 6 . M. Liu, K. Zhu, J. Gu, L. Shen, X. Tang, N. Sun, and D. Z. Pan, \"Towards decrypting the art of analog layout, placement quality prediction via transfer learning,\" in Proc. DATE, 2020, pp. 1--6.","journal-title":"Proc. DATE"},{"key":"e_1_3_2_1_20_1","volume-title":"GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learning,\" arXiv preprint arXiv:2005.00406","author":"Wang H.","year":"2020","unstructured":"H. Wang , K. Wang , J. Yang , L. Shen , N. Sun , H.-S. Lee , and S. Han , \" GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learning,\" arXiv preprint arXiv:2005.00406 , 2020 . H. Wang, K. Wang, J. Yang, L. Shen, N. Sun, H.-S. Lee, and S. Han, \"GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learning,\" arXiv preprint arXiv:2005.00406, 2020."},{"key":"e_1_3_2_1_21_1","volume-title":"Graph attention networks,\" arXiv preprint arXiv:1710.10903","author":"Veli\u010dkovi\u0107 P.","year":"2017","unstructured":"P. Veli\u010dkovi\u0107 , G. Cucurull , A. Casanova , A. Romero , P. Lio , and Y. Bengio , \" Graph attention networks,\" arXiv preprint arXiv:1710.10903 , 2017 . P. Veli\u010dkovi\u0107, G. Cucurull, A. Casanova, A. Romero, P. Lio, and Y. Bengio, \"Graph attention networks,\" arXiv preprint arXiv:1710.10903, 2017."},{"key":"e_1_3_2_1_22_1","first-page":"4800","volume-title":"Hierarchical graph representation learning with differentiable pooling,\" in Advances in neural information processing systems","author":"Ying Z.","year":"2018","unstructured":"Z. Ying , J. You , C. Morris , X. Ren , W. Hamilton , and J. Leskovec , \" Hierarchical graph representation learning with differentiable pooling,\" in Advances in neural information processing systems , 2018 , pp. 4800 -- 4810 . Z. Ying, J. You, C. Morris, X. Ren, W. Hamilton, and J. Leskovec, \"Hierarchical graph representation learning with differentiable pooling,\" in Advances in neural information processing systems, 2018, pp. 4800--4810."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2019.2933554"},{"key":"e_1_3_2_1_24_1","first-page":"9211","volume-title":"CVPR","author":"Gong L.","year":"2019","unstructured":"L. Gong and Q. Cheng , \" Exploiting edge features for graph neural networks,\" in Proc . CVPR , 2019 , pp. 9211 -- 9219 . L. Gong and Q. Cheng, \"Exploiting edge features for graph neural networks,\" in Proc. CVPR, 2019, pp. 9211--9219."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"}],"event":{"name":"ICCAD '20: IEEE\/ACM International Conference on Computer-Aided Design","location":"Virtual Event USA","acronym":"ICCAD '20","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA","IEEE CS"]},"container-title":["Proceedings of the 39th International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3400302.3415624","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3400302.3415624","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:31:41Z","timestamp":1750195901000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3400302.3415624"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,2]]},"references-count":25,"alternative-id":["10.1145\/3400302.3415624","10.1145\/3400302"],"URL":"https:\/\/doi.org\/10.1145\/3400302.3415624","relation":{},"subject":[],"published":{"date-parts":[[2020,11,2]]},"assertion":[{"value":"2020-12-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}