{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T09:32:20Z","timestamp":1761989540409,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":31,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,11,2]],"date-time":"2020-11-02T00:00:00Z","timestamp":1604275200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Strategic Priority Research Program of Chinese Academy of Sciences","award":["XDC05030201"],"award-info":[{"award-number":["XDC05030201"]}]},{"name":"National Natural Science Foundation of China","award":["61874124, 61876173, 61532017, 61772300, 61902375"],"award-info":[{"award-number":["61874124, 61876173, 61532017, 61772300, 61902375"]}]},{"name":"YESS hip program","award":["YESS2016qnrc001"],"award-info":[{"award-number":["YESS2016qnrc001"]}]},{"name":"National Key Research and Development Program of China","award":["2018AAA0102700"],"award-info":[{"award-number":["2018AAA0102700"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,11,2]]},"DOI":"10.1145\/3400302.3415645","type":"proceedings-article","created":{"date-parts":[[2020,12,18]],"date-time":"2020-12-18T01:20:55Z","timestamp":1608254455000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":26,"title":["DeepBurning-GL"],"prefix":"10.1145","author":[{"given":"Shengwen","family":"Liang","sequence":"first","affiliation":[{"name":"University of Chinese Academy of Sciences"}]},{"given":"Cheng","family":"Liu","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences"}]},{"given":"Ying","family":"Wang","sequence":"additional","affiliation":[{"name":"University of Chinese Academy of Sciences"}]},{"given":"Huawei","family":"Li","sequence":"additional","affiliation":[{"name":"University of Chinese Academy of Sciences"}]},{"given":"Xiaowei","family":"Li","sequence":"additional","affiliation":[{"name":"University of Chinese Academy of Sciences"}]}],"member":"320","published-online":{"date-parts":[[2020,12,17]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2644865.2541967"},{"key":"e_1_3_2_1_2_1","unstructured":"Matthias Fey and Jan Eric Lenssen. 2019. Fast Graph Representation Learning with PyTorch Geometric. arXiv:1903.02428 [cs.LG]  Matthias Fey and Jan Eric Lenssen. 2019. Fast Graph Representation Learning with PyTorch Geometric. arXiv:1903.02428 [cs.LG]"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2017.25"},{"key":"e_1_3_2_1_4_1","volume-title":"Graphicionado: A High-Performance and Energy-Efficient Accelerator for Graph Analytics. In &lt;u&gt;The 49th Annual IEEE\/ACM International Symposium on Microarchitecture&lt;\/u&gt","author":"Ham Tae Jun","year":"2016","unstructured":"Tae Jun Ham , Lisa Wu , Narayanan Sundaram , Nadathur Satish , and Margaret Martonosi . 2016 . Graphicionado: A High-Performance and Energy-Efficient Accelerator for Graph Analytics. In &lt;u&gt;The 49th Annual IEEE\/ACM International Symposium on Microarchitecture&lt;\/u&gt ; (Taipei, Taiwan ) &lt;u&gt;(MICRO-49).&lt;\/u&gt; IEEE Press , Article 56, 13 pages. Tae Jun Ham, Lisa Wu, Narayanan Sundaram, Nadathur Satish, and Margaret Martonosi. 2016. Graphicionado: A High-Performance and Energy-Efficient Accelerator for Graph Analytics. In &lt;u&gt;The 49th Annual IEEE\/ACM International Symposium on Microarchitecture&lt;\/u&gt; (Taipei, Taiwan) &lt;u&gt;(MICRO-49).&lt;\/u&gt; IEEE Press, Article 56, 13 pages."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317829"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/3292500.3330941"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3014632"},{"volume-title":"Cognitive SSD: A Deep Learning Engine for in-Storage Data Retrieval. In &lt;u&gt;Proceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference&lt;\/u&gt","author":"Liang Shengwen","key":"e_1_3_2_1_8_1","unstructured":"Shengwen Liang , Ying Wang , Youyou Lu , Zhe Yang , Huawei Li , and Xiaowei Li. 2019. Cognitive SSD: A Deep Learning Engine for in-Storage Data Retrieval. In &lt;u&gt;Proceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference&lt;\/u&gt ; (Renton, WA , USA) &lt;u&gt;(USENIX ATC '19).&lt;\/u&gt; USENIX Association , USA, 395--410. Shengwen Liang, Ying Wang, Youyou Lu, Zhe Yang, Huawei Li, and Xiaowei Li. 2019. Cognitive SSD: A Deep Learning Engine for in-Storage Data Retrieval. In &lt;u&gt;Proceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference&lt;\/u&gt; (Renton, WA, USA) &lt;u&gt;(USENIX ATC '19).&lt;\/u&gt; USENIX Association, USA, 395--410."},{"key":"e_1_3_2_1_9_1","volume-title":"Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay. &lt;u&gt;CoRR&lt;\/u&gt","author":"Liu Cheng","year":"2015","unstructured":"Cheng Liu , Ho-Cheung Ng , and Hayden Kwok-Hay So . 2015. Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay. &lt;u&gt;CoRR&lt;\/u&gt ; abs\/1509.00042 ( 2015 ). arXiv:1509.00042 http:\/\/arxiv.org\/abs\/1509.00042 Cheng Liu, Ho-Cheung Ng, and Hayden Kwok-Hay So. 2015. Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay. &lt;u&gt;CoRR&lt;\/u&gt; abs\/1509.00042 (2015). arXiv:1509.00042 http:\/\/arxiv.org\/abs\/1509.00042"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"crossref","unstructured":"C. Liu H. Ng and H. K. So. 2015. QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay. In &lt;u&gt;2015 International Conference on Field Programmable Technology (FPT).&lt;\/u&gt; 56--63.  C. Liu H. Ng and H. K. So. 2015. QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay. In &lt;u&gt;2015 International Conference on Field Programmable Technology (FPT).&lt;\/u&gt; 56--63.","DOI":"10.1109\/FPT.2015.7393130"},{"key":"e_1_3_2_1_11_1","volume":"201","author":"Ma Y.","unstructured":"Y. Ma , Y. Cao , S. Vrudhula , and J. Seo. 201 7. An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. In &lt;u&gt;2017 27th International Conference on Field Programmable Logic and Applications (FPL).&lt;\/u&gt; 1--8. Y. Ma, Y. Cao, S. Vrudhula, and J. Seo. 2017. An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. In &lt;u&gt;2017 27th International Conference on Field Programmable Logic and Applications (FPL).&lt;\/u&gt; 1--8.","journal-title":"J. Seo."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056824"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3397271.3401092"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/3292500.3330855"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"R. Pinkham S. Zeng and Z. Zhang. 2020. QuickNN: Memory and Performance Optimization of k-d Tree Based Nearest Neighbor Search for 3D Point Clouds. In &lt;u&gt;2020 IEEE International Symposium on High Performance Computer Architecture (HPCA).&lt;\/u&gt; 180--192.  R. Pinkham S. Zeng and Z. Zhang. 2020. QuickNN: Memory and Performance Optimization of k-d Tree Based Nearest Neighbor Search for 3D Point Clouds. In &lt;u&gt;2020 IEEE International Symposium on High Performance Computer Architecture (HPCA).&lt;\/u&gt; 180--192.","DOI":"10.1109\/HPCA47549.2020.00024"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3219819.3220077"},{"key":"e_1_3_2_1_17_1","volume-title":"Chenkai Shao, Asit Mishra, and Hadi Esmaeilzadeh.","author":"Sharma Hardik","year":"2016","unstructured":"Hardik Sharma , Jongse Park , Divya Mahajan , Emmanuel Amaro , Joon Kyung Kim , Chenkai Shao, Asit Mishra, and Hadi Esmaeilzadeh. 2016 . From High-Level Deep Neural Models to FPGAs. In &lt;u&gt;The 49th Annual IEEE\/ACM International Symposium on Microarchitecture&lt;\/u&gt; (Taipei, Taiwan) &lt;u&gt;(MICRO-49).&lt;\/u&gt; IEEE Press , Article 17, 12 pages. Hardik Sharma, Jongse Park, Divya Mahajan, Emmanuel Amaro, Joon Kyung Kim, Chenkai Shao, Asit Mishra, and Hadi Esmaeilzadeh. 2016. From High-Level Deep Neural Models to FPGAs. In &lt;u&gt;The 49th Annual IEEE\/ACM International Symposium on Microarchitecture&lt;\/u&gt; (Taipei, Taiwan) &lt;u&gt;(MICRO-49).&lt;\/u&gt; IEEE Press, Article 17, 12 pages."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897995"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"crossref","unstructured":"S. I. Venieris and C. Bouganis. 2016. fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs. In &lt;u&gt;2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).&lt;\/u&gt; 40--47.  S. I. Venieris and C. Bouganis. 2016. fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs. In &lt;u&gt;2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).&lt;\/u&gt; 40--47.","DOI":"10.1109\/FCCM.2016.22"},{"key":"e_1_3_2_1_20_1","unstructured":"Minjie Wang Lingfan Yu Da Zheng Quan Gan Yu Gai Zihao Ye Mufei Li Jinjing Zhou Qi Huang Chao Ma Ziyue Huang Qipeng Guo Hao Zhang Haibin Lin Junbo Zhao Jinyang Li Alexander Smola and Zheng Zhang. 2019. Deep Graph Library: Towards Efficient and Scalable Deep Learning on Graphs. arXiv:1909.01315 [cs.LG]  Minjie Wang Lingfan Yu Da Zheng Quan Gan Yu Gai Zihao Ye Mufei Li Jinjing Zhou Qi Huang Chao Ma Ziyue Huang Qipeng Guo Hao Zhang Haibin Lin Junbo Zhao Jinyang Li Alexander Smola and Zheng Zhang. 2019. Deep Graph Library: Towards Efficient and Scalable Deep Learning on Graphs. arXiv:1909.01315 [cs.LG]"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/3308558.3313562"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/3326362"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898003"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375306"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2020.2970395"},{"key":"e_1_3_2_1_26_1","volume-title":"HyGCN: A GCN Accelerator with Hybrid Architecture. ArXiv abs\/2001.02514","author":"Yan Mingyu","year":"2020","unstructured":"Mingyu Yan , Lei Deng , Xing Hu , Ling Liang , Yujing Feng , Xiaochun Ye , Zhimin Zhang , Dongrui Fan , and Yuan Xie . 2020. HyGCN: A GCN Accelerator with Hybrid Architecture. ArXiv abs\/2001.02514 ( 2020 ). Mingyu Yan, Lei Deng, Xing Hu, Ling Liang, Yujing Feng, Xiaochun Ye, Zhimin Zhang, Dongrui Fan, and Yuan Xie. 2020. HyGCN: A GCN Accelerator with Hybrid Architecture. ArXiv abs\/2001.02514 (2020)."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/3292500.3340404"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/3219819.3219890"},{"key":"e_1_3_2_1_29_1","volume-title":"GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms. &lt;u&gt;ArXiv&lt;\/u&gt","author":"Zeng Hanqing","year":"2001","unstructured":"Hanqing Zeng and Viktor Prasanna . 2019. GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms. &lt;u&gt;ArXiv&lt;\/u&gt ; abs\/ 2001 .02498 (2019). Hanqing Zeng and Viktor Prasanna. 2019. GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms. &lt;u&gt;ArXiv&lt;\/u&gt; abs\/2001.02498 (2019)."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967011"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240801"}],"event":{"name":"ICCAD '20: IEEE\/ACM International Conference on Computer-Aided Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA","IEEE CS"],"location":"Virtual Event USA","acronym":"ICCAD '20"},"container-title":["Proceedings of the 39th International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3400302.3415645","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3400302.3415645","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:31:41Z","timestamp":1750195901000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3400302.3415645"}},"subtitle":["an automated framework for generating graph neural network accelerators"],"short-title":[],"issued":{"date-parts":[[2020,11,2]]},"references-count":31,"alternative-id":["10.1145\/3400302.3415645","10.1145\/3400302"],"URL":"https:\/\/doi.org\/10.1145\/3400302.3415645","relation":{},"subject":[],"published":{"date-parts":[[2020,11,2]]},"assertion":[{"value":"2020-12-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}