{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:25:43Z","timestamp":1750220743629,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,11,2]],"date-time":"2020-11-02T00:00:00Z","timestamp":1604275200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,11,2]]},"DOI":"10.1145\/3400302.3415772","type":"proceedings-article","created":{"date-parts":[[2020,12,18]],"date-time":"2020-12-18T01:20:55Z","timestamp":1608254455000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["On EDA solutions for reconfigurable memory-centric AI edge applications"],"prefix":"10.1145","author":[{"given":"Hung-Ming","family":"Chen","sequence":"first","affiliation":[{"name":"National Chiao Tung University, Hsinchu City, Taiwan, R.O.C."}]},{"given":"Chia-Lin","family":"Hu","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu City, Taiwan, R.O.C."}]},{"given":"Kang-Yu","family":"Chang","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu City, Taiwan, R.O.C."}]},{"given":"Alexandra","family":"K\u00fcster","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu City, Taiwan, R.O.C. and RWTH Aachen University, Germany"}]},{"given":"Yu-Hsien","family":"Lin","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu City, Taiwan, R.O.C."}]},{"given":"Po-Shen","family":"Kuo","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu City, Taiwan, R.O.C."}]},{"given":"Wei-Tung","family":"Chao","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu City, Taiwan, R.O.C."}]},{"given":"Bo-Cheng","family":"Lai","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu City, Taiwan, R.O.C."}]},{"given":"Chien-Nan","family":"Liu","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu City, Taiwan, R.O.C."}]},{"given":"Shyh-Jye","family":"Jou","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu City, Taiwan, R.O.C."}]}],"member":"320","published-online":{"date-parts":[[2020,12,17]]},"reference":[{"volume-title":"Automation Test in Europe Conference Exhibition. 1--6.","author":"Barajas E.","key":"e_1_3_2_1_1_1","unstructured":"E. Barajas , R. Cosculluela , D. Coutinho , D. Mateo , J. L. Gonzalez , I. Cairo , S. Banda , and M. Ikeda . 2007. Behavioral Modeling of Delay-Locked Loops and its Application to Jitter Optimization in Ultra Wide-Band Impulse Radio Systems. In 2007 Design , Automation Test in Europe Conference Exhibition. 1--6. E. Barajas, R. Cosculluela, D. Coutinho, D. Mateo, J. L. Gonzalez, I. Cairo, S. Banda, and M. Ikeda. 2007. Behavioral Modeling of Delay-Locked Loops and its Application to Jitter Optimization in Ultra Wide-Band Impulse Radio Systems. In 2007 Design, Automation Test in Europe Conference Exhibition. 1--6."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"volume-title":"2018 IEEE International Solid - State Circuits Conference - (ISSCC). 488--490","author":"Biswas A.","key":"e_1_3_2_1_3_1","unstructured":"A. Biswas and A. P. Chandrakasan . 2018. Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications . In 2018 IEEE International Solid - State Circuits Conference - (ISSCC). 488--490 . A. Biswas and A. P. Chandrakasan. 2018. Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications. In 2018 IEEE International Solid - State Circuits Conference - (ISSCC). 488--490."},{"volume-title":"2016 IEEE International Symposium on Circuits and Systems (ISCAS). 2310--2313","author":"Chen P.","key":"e_1_3_2_1_4_1","unstructured":"P. Chen and S. Yu . 2016. Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing . In 2016 IEEE International Symposium on Circuits and Systems (ISCAS). 2310--2313 . P. Chen and S. Yu. 2016. Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing. In 2016 IEEE International Symposium on Circuits and Systems (ISCAS). 2310--2313."},{"key":"e_1_3_2_1_5_1","volume-title":"The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design. In 2020 IEEE International Solid - State Circuits Conference - (ISSCC). https:\/\/arxiv.org\/pdf\/1911","author":"Dean J.","year":"2020","unstructured":"J. Dean . 2020 . The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design. In 2020 IEEE International Solid - State Circuits Conference - (ISSCC). https:\/\/arxiv.org\/pdf\/1911 .05289.pdf J. Dean. 2020. The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design. In 2020 IEEE International Solid - State Circuits Conference - (ISSCC). https:\/\/arxiv.org\/pdf\/1911.05289.pdf"},{"volume-title":"2018 IEEE International Solid - State Circuits Conference - (ISSCC). 490--492","author":"Gonugondla S. K.","key":"e_1_3_2_1_6_1","unstructured":"S. K. Gonugondla , M. Kang , and N. Shanbhag . 2018. A 42pJ\/decision 3.12TOPS\/W robust in-memory machine learning classifier with on-chip training . In 2018 IEEE International Solid - State Circuits Conference - (ISSCC). 490--492 . S. K. Gonugondla, M. Kang, and N. Shanbhag. 2018. A 42pJ\/decision 3.12TOPS\/W robust in-memory machine learning classifier with on-chip training. In 2018 IEEE International Solid - State Circuits Conference - (ISSCC). 490--492."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2143870"},{"volume-title":"Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO '52)","author":"Huangfu W.","key":"e_1_3_2_1_8_1","unstructured":"W. Huangfu , X. Li , S. Li , X. Hu , P. Gu , and Y. Xie . 2019. MEDAL: Scalable DIMM Based Near Data Processing Accelerator for DNA Seeding Algorithm . In Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO '52) . 587--599. W. Huangfu, X. Li, S. Li, X. Hu, P. Gu, and Y. Xie. 2019. MEDAL: Scalable DIMM Based Near Data Processing Accelerator for DNA Seeding Algorithm. In Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO '52). 587--599."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2845883"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2782087"},{"key":"e_1_3_2_1_11_1","first-page":"1274","article-title":"Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing","volume":"36","author":"Lin M. P.-H.","year":"2017","unstructured":"M. P.-H. Lin , V. W.-H. Hsiao , C.-Y. Lin , and N.-C. Chen . 2017 . Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing . IEEE TCAD 36 , 8 (2017), 1274 -- 1286 . M. P.-H. Lin, V. W.-H. Hsiao, C.-Y. Lin, and N.-C. Chen. 2017. Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing. IEEE TCAD 36, 8 (2017), 1274--1286.","journal-title":"IEEE TCAD"},{"key":"e_1_3_2_1_12_1","unstructured":"V. Seshadri and O. Mutlu. 2019. In-DRAM Bulk Bitwise Execution Engine.  V. Seshadri and O. Mutlu. 2019. In-DRAM Bulk Bitwise Execution Engine."},{"volume-title":"Outrageously Large Neural Networks: The Sparsely-Gated Mixture-of-experts Layer. In 2017 International Conference on Learning Representations (ICLR).","author":"Shazeer N.","key":"e_1_3_2_1_13_1","unstructured":"N. Shazeer , A. Mirhoseini , K. Maziarz , A. Davis , Q. Le , G. Hinton , and J. Dean . 2017 . Outrageously Large Neural Networks: The Sparsely-Gated Mixture-of-experts Layer. In 2017 International Conference on Learning Representations (ICLR). N. Shazeer, A. Mirhoseini, K. Maziarz, A. Davis, Q. Le, G. Hinton, and J. Dean. 2017. Outrageously Large Neural Networks: The Sparsely-Gated Mixture-of-experts Layer. In 2017 International Conference on Learning Representations (ICLR)."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2952773"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675787"}],"event":{"name":"ICCAD '20: IEEE\/ACM International Conference on Computer-Aided Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA","IEEE CS"],"location":"Virtual Event USA","acronym":"ICCAD '20"},"container-title":["Proceedings of the 39th International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3400302.3415772","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3400302.3415772","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:38:42Z","timestamp":1750199922000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3400302.3415772"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,2]]},"references-count":15,"alternative-id":["10.1145\/3400302.3415772","10.1145\/3400302"],"URL":"https:\/\/doi.org\/10.1145\/3400302.3415772","relation":{},"subject":[],"published":{"date-parts":[[2020,11,2]]},"assertion":[{"value":"2020-12-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}