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Embed. Comput. Syst."],"published-print":{"date-parts":[[2020,7,31]]},"abstract":"<jats:p>Static random access memory\u2013 (SRAM) based field programmable gate arrays (FPGAs) are currently facing challenges of limited capacity and high leakage power. To solve this problem, non-volatile memory (NVM) is proposed as the alternative to build non-volatile FPGAs (NVFPGAs). Even though the feasibility of NVFPGA has been confirmed, the utilization of multiple level cells (MLCs) has not been fully exploited yet.<\/jats:p>\n          <jats:p>In this article, we study architecture of MLC-based NVFPGAs, and propose five cluster structures. To give detailed comparisons and extensive discussions, we conduct experiments for area, performance and leakage power evaluation. Based on explorations of the characteristics of MLC-based NVFPGAs, we further present MLC-aware timing-driven packing method to improve delay. In critical paths, our proposed method reduces the overhead of the additional delay in slow MLC cells. Experiments show that, compared to SRAM-based FPGAs, the proposed architecture with the proposed CAD flow can reduce the area, critical path delay and leakage power by 31%, 10%, and 95%, respectively.<\/jats:p>","DOI":"10.1145\/3400885","type":"journal-article","created":{"date-parts":[[2020,7,12]],"date-time":"2020-07-12T22:05:03Z","timestamp":1594591503000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Applying Multiple Level Cell to Non-volatile FPGAs"],"prefix":"10.1145","volume":"19","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0617-5613","authenticated-orcid":false,"given":"Ke","family":"Liu","sequence":"first","affiliation":[{"name":"School of Computer Science and Technology, Shandong University, China"}]},{"given":"Mengying","family":"Zhao","sequence":"additional","affiliation":[{"name":"School of Computer Science and Technology, Shandong University, China"}]},{"given":"Lei","family":"Ju","sequence":"additional","affiliation":[{"name":"School of Computer Science and Technology, Shandong University, China"}]},{"given":"Zhiping","family":"Jia","sequence":"additional","affiliation":[{"name":"School of Computer Science and Technology, Shandong University, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4029-4034","authenticated-orcid":false,"given":"Jingtong","family":"Hu","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Pittsburgh, USA"}]},{"given":"Chun Jason","family":"Xue","sequence":"additional","affiliation":[{"name":"Department of Computer Science, City University of Hong Kong, Hong Kong, China"}]}],"member":"320","published-online":{"date-parts":[[2020,7,12]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1997.606687"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897987"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840857"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718327"},{"key":"e_1_2_1_5_1","volume-title":"Proceedings of the International Conference on VLSI and System-on-Chip (VLSI-SoC\u201912)","author":"Gaillardon Pierre-Emmanuel","year":"2012","unstructured":"Pierre-Emmanuel Gaillardon , Davide Sacchetto , Shashikanth Bobba , Yusuf Leblebici , and Giovanni De Micheli . 2012 . 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Weisheng Zhao, Eric Belhaire, Virgile Javerliac, Claude Chappert, and Bernard Dieny. 2006. Evaluation of a non-volatile FPGA based on MRAM technology. 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