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However, finding an optimized application-specific NoC architecture is a challenging task due to the huge design space.<\/jats:p>\n          <jats:p>This article proposes to apply machine learning approaches for this task. Using graph rewriting, the NoC Design Space Exploration (DSE) is modelled as a Markov Decision Process (MDP). Monte Carlo Tree Search (MCTS), a technique from reinforcement learning, is used as search heuristic. Our experimental results show that\u2014with the same cost function and exploration budget\u2014MCTS finds superior NoC architectures compared to Simulated Annealing (SA) and a Genetic Algorithm\u00a0(GA). However, the NoC DSE process suffers from the high computation time due to expensive cycle-accurate SystemC simulations for latency estimation. This article therefore additionally proposes to replace latency simulation by fast latency estimation using a Recurrent Neural Network (RNN). The designed RNN is sufficiently general for latency estimation on arbitrary NoC architectures. Our experiments show that compared to SystemC simulation, the RNN-based latency estimation offers a similar speed-up as the widely used Queuing Theory (QT). Yet, in terms of estimation accuracy and fidelity, the RNN is superior to QT, especially for high-traffic scenarios. When replacing SystemC simulations with the RNN estimation, the obtained solution quality decreases only slightly, whereas it suffers significantly when QT is used.<\/jats:p>","DOI":"10.1145\/3403584","type":"journal-article","created":{"date-parts":[[2020,8,28]],"date-time":"2020-08-28T10:05:44Z","timestamp":1598609144000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs"],"prefix":"10.1145","volume":"25","author":[{"given":"Yong","family":"Hu","sequence":"first","affiliation":[{"name":"Chair of EDA, Technical University of Munich, Munich, Germany"}]},{"given":"Marcel","family":"Mettler","sequence":"additional","affiliation":[{"name":"Chair of EDA, Technical University of Munich, Munich, Germany"}]},{"given":"Daniel","family":"Mueller-Gritschneder","sequence":"additional","affiliation":[{"name":"Chair of EDA, Technical University of Munich, Munich, Germany"}]},{"given":"Thomas","family":"Wild","sequence":"additional","affiliation":[{"name":"Chair of Integrated Systems, Technical University of Munich, Munich, Germany"}]},{"given":"Andreas","family":"Herkersdorf","sequence":"additional","affiliation":[{"name":"Chair of Integrated Systems, Technical University of Munich, Munich, Germany"}]},{"given":"Ulf","family":"Schlichtmann","sequence":"additional","affiliation":[{"name":"Chair of EDA, Technical University of Munich, Munich, Germany"}]}],"member":"320","published-online":{"date-parts":[[2020,8,28]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"FreeMarker Code Generation Engine. 2019. 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