{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,28]],"date-time":"2025-11-28T17:23:07Z","timestamp":1764350587770,"version":"3.41.0"},"reference-count":34,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2020,8,21]],"date-time":"2020-08-21T00:00:00Z","timestamp":1597968000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2020,9,30]]},"abstract":"<jats:p>Field programmable gate array (FPGA) is ubiquitous nowadays and is applied to many areas. Dynamic partial reconfiguration (DPR) is introduced to most modern FPGAs, enabling changing the function of a part of the FPGA by dynamically loading new bitstreams to the logic regions without affecting the function of other parts of the FPGA. However, delivering the powerful capacity of the DPR FPGA to the user depends on the efficient partitioning and scheduling technology. This article proposes the module merging technique for the partitioning and scheduling problem to reduce the reconfiguration overhead and improve the schedule performance. An exact approach based on the integer linear programming (ILP) for the partitioning and scheduling problem with module merging is proposed. The ILP-based approach is capable of solving the problem optimally, and can be used to further improve the performance of schedules produced by other non-optimal algorithms; however, it is time-consuming to solve large-scale problems. Therefore, a K-sliced-ILP algorithm based on the methodology of divide-and-conquer is proposed, which is able to reduce the time complexity significantly with the solution quality being degraded marginally. Experiments are carried out with a set of real-life applications, and the result demonstrates the effectiveness of the proposed methods.<\/jats:p>","DOI":"10.1145\/3403702","type":"journal-article","created":{"date-parts":[[2020,8,21]],"date-time":"2020-08-21T23:00:18Z","timestamp":1598050818000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAs"],"prefix":"10.1145","volume":"13","author":[{"given":"Qi","family":"Tang","sequence":"first","affiliation":[{"name":"National University of Defense Technology, Changsha, Hunan, China"}]},{"given":"Zhe","family":"Wang","sequence":"additional","affiliation":[{"name":"Hunan University, China and National University of Defense Technology, Changsha, Hunan, China"}]},{"given":"Biao","family":"Guo","sequence":"additional","affiliation":[{"name":"Hunan University, China and National University of Defense Technology, Changsha, Hunan, China"}]},{"given":"Li-Hua","family":"Zhu","sequence":"additional","affiliation":[{"name":"Hunan University, China and National University of Defense Technology, Changsha, Hunan, China"}]},{"given":"Ji-Bo","family":"Wei","sequence":"additional","affiliation":[{"name":"National University of Defense Technology, Changsha, Hunan, China"}]}],"member":"320","published-online":{"date-parts":[[2020,8,21]]},"reference":[{"unstructured":"GUROBI. Retrieved from http:\/\/www.gurobi.com.  GUROBI. Retrieved from http:\/\/www.gurobi.com.","key":"e_1_2_1_1_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_2_1","DOI":"10.1109\/TVLSI.2008.2003490"},{"doi-asserted-by":"publisher","key":"e_1_2_1_3_1","DOI":"10.1109\/TVLSI.2006.886411"},{"doi-asserted-by":"publisher","key":"e_1_2_1_4_1","DOI":"10.1109\/TCAD.2011.2138140"},{"doi-asserted-by":"publisher","key":"e_1_2_1_5_1","DOI":"10.1109\/LES.2011.2115991"},{"volume-title":"Proceedings of the Real-Time Systems Symposium (RTSS). 1--12","year":"2017","author":"Biondi Alessandro","key":"e_1_2_1_6_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_7_1","DOI":"10.1109\/AHS.2017.8046375"},{"unstructured":"Louis-Claude Canon and Mohamad El Sayah. 2019. A comparison of random task graph generation methods for scheduling problems. (2019). arxiv:arXiv:1902.05808v1  Louis-Claude Canon and Mohamad El Sayah. 2019. A comparison of random task graph generation methods for scheduling problems. (2019). arxiv:arXiv:1902.05808v1","key":"e_1_2_1_8_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_9_1","DOI":"10.1109\/IPDPSW.2014.32"},{"key":"e_1_2_1_10_1","article-title":"Integrated optimization of partitioning, scheduling, and floorplanning for partially dynamically reconfigurable systems","volume":"0070","author":"Chen Song","year":"2018","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"doi-asserted-by":"publisher","key":"e_1_2_1_11_1","DOI":"10.1145\/2611562"},{"doi-asserted-by":"publisher","key":"e_1_2_1_12_1","DOI":"10.1109\/FPL.2011.40"},{"doi-asserted-by":"publisher","key":"e_1_2_1_13_1","DOI":"10.1109\/TCAD.2009.2015739"},{"volume-title":"Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014 (2015","year":"2015","author":"Dai Guohao","key":"e_1_2_1_14_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_15_1","DOI":"10.1109\/ReConFig.2015.7393328"},{"doi-asserted-by":"publisher","key":"e_1_2_1_16_1","DOI":"10.1109\/AHS.2013.6604225"},{"doi-asserted-by":"publisher","key":"e_1_2_1_17_1","DOI":"10.1145\/2429384.2429491"},{"doi-asserted-by":"crossref","unstructured":"Ahmed Kamaleldin Islam Ahmed Abulfattah M. Obeid Ahmed Shalash Yehea Ismail and Hassan Mostafa. 2017. A cost-effective dynamic partial reconfiguration implementation flow for Xilinx FPGA. In IEEE International NEW Generation of Circuits and Systems. 281--284. DOI:https:\/\/doi.org\/10.1109\/NGCAS.2017.17  Ahmed Kamaleldin Islam Ahmed Abulfattah M. Obeid Ahmed Shalash Yehea Ismail and Hassan Mostafa. 2017. A cost-effective dynamic partial reconfiguration implementation flow for Xilinx FPGA. In IEEE International NEW Generation of Circuits and Systems. 281--284. DOI:https:\/\/doi.org\/10.1109\/NGCAS.2017.17","key":"e_1_2_1_18_1","DOI":"10.1109\/NGCAS.2017.17"},{"doi-asserted-by":"publisher","key":"e_1_2_1_19_1","DOI":"10.1109\/LPT.2014.2337888"},{"doi-asserted-by":"publisher","key":"e_1_2_1_20_1","DOI":"10.1109\/ICCD.2014.6974721"},{"doi-asserted-by":"publisher","key":"e_1_2_1_21_1","DOI":"10.1109\/TCAD.2015.2513673"},{"volume-title":"Proceedings of the 2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017. (2017","year":"2017","author":"Pezzarossa L.","key":"e_1_2_1_22_1"},{"volume-title":"Proceedings of the 2016 IEEE 30th International Parallel and Distributed Processing Symposium, IPDPS 2016 (2016","year":"2016","author":"Purgato Andrea","key":"e_1_2_1_23_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_24_1","DOI":"10.5555\/2650280.2650381"},{"doi-asserted-by":"publisher","key":"e_1_2_1_25_1","DOI":"10.1109\/TVLSI.2016.2562361"},{"doi-asserted-by":"publisher","key":"e_1_2_1_26_1","DOI":"10.1145\/1629435.1629480"},{"doi-asserted-by":"publisher","key":"e_1_2_1_27_1","DOI":"10.1145\/3182183"},{"doi-asserted-by":"publisher","key":"e_1_2_1_28_1","DOI":"10.1109\/LES.2015.2396069"},{"doi-asserted-by":"publisher","key":"e_1_2_1_29_1","DOI":"10.1016\/j.jpdc.2016.11.012"},{"doi-asserted-by":"publisher","key":"e_1_2_1_30_1","DOI":"10.1109\/TPDS.2016.2599166"},{"doi-asserted-by":"crossref","unstructured":"Qi Tang Li-Hua Zhu Jin Lian Li Zhou and Ji-Bo Wei. 2020. An efficient multi-functional duplication-based scheduling framework for multiprocessor systems. The Journal of Supercomputing 9 (2020). DOI:https:\/\/doi.org\/10.1007\/s11227-020-03208-y  Qi Tang Li-Hua Zhu Jin Lian Li Zhou and Ji-Bo Wei. 2020. An efficient multi-functional duplication-based scheduling framework for multiprocessor systems. The Journal of Supercomputing 9 (2020). DOI:https:\/\/doi.org\/10.1007\/s11227-020-03208-y","key":"e_1_2_1_31_1","DOI":"10.1007\/s11227-020-03208-y"},{"doi-asserted-by":"publisher","key":"e_1_2_1_32_1","DOI":"10.1016\/j.jpdc.2019.12.012"},{"doi-asserted-by":"publisher","key":"e_1_2_1_33_1","DOI":"10.1145\/3193827"},{"doi-asserted-by":"publisher","key":"e_1_2_1_34_1","DOI":"10.1145\/1698759.1698763"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3403702","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3403702","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:38:22Z","timestamp":1750199902000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3403702"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8,21]]},"references-count":34,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2020,9,30]]}},"alternative-id":["10.1145\/3403702"],"URL":"https:\/\/doi.org\/10.1145\/3403702","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2020,8,21]]},"assertion":[{"value":"2020-02-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-05-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-08-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}