{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:23:08Z","timestamp":1750220588177,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,8,17]],"date-time":"2020-08-17T00:00:00Z","timestamp":1597622400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,8,17]]},"DOI":"10.1145\/3404397.3404448","type":"proceedings-article","created":{"date-parts":[[2020,8,9]],"date-time":"2020-08-09T03:54:26Z","timestamp":1596945266000},"page":"1-11","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["HCAPP: Scalable Power Control for Heterogeneous 2.5D Integrated Systems"],"prefix":"10.1145","author":[{"given":"Kramer","family":"Straube","sequence":"first","affiliation":[{"name":"University of California Davis, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jason","family":"Lowe-Power","sequence":"additional","affiliation":[{"name":"University of California Davis, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christopher","family":"Nitta","sequence":"additional","affiliation":[{"name":"University of California Davis, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthew","family":"Farrens","sequence":"additional","affiliation":[{"name":"University of California Davis, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Venkatesh","family":"Akella","sequence":"additional","affiliation":[{"name":"University of California Davis, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,8,17]]},"reference":[{"volume-title":"Cores Meet 14 nm I\/O Die. https:\/\/www.anandtech.com\/show\/13560\/amd-unveils-chiplet-design-approach-7nm-zen-2-cores-meets-14-nm-io-die. Accessed: 2019-01-17","key":"e_1_3_2_1_1_1","unstructured":"[n.d.]. AMD Unveils \u2019Chiplet\u2019 Design Approach: 7nm Zen 2 Cores Meet 14 nm I\/O Die. https:\/\/www.anandtech.com\/show\/13560\/amd-unveils-chiplet-design-approach-7nm-zen-2-cores-meets-14-nm-io-die. Accessed: 2019-01-17 . [n.d.]. AMD Unveils \u2019Chiplet\u2019 Design Approach: 7nm Zen 2 Cores Meet 14 nm I\/O Die. https:\/\/www.anandtech.com\/show\/13560\/amd-unveils-chiplet-design-approach-7nm-zen-2-cores-meets-14-nm-io-die. Accessed: 2019-01-17."},{"key":"e_1_3_2_1_2_1","unstructured":"[n.d.]. Intel\u2019s Architecture Day 2018: The Future of Core Intel GPUs 10nm and Hybrid x86. https:\/\/www.anandtech.com\/show\/13699\/intel-architecture-day-2018-core-future-hybrid-x86\/6. Accessed: 2019-01-17.  [n.d.]. Intel\u2019s Architecture Day 2018: The Future of Core Intel GPUs 10nm and Hybrid x86. https:\/\/www.anandtech.com\/show\/13699\/intel-architecture-day-2018-core-future-hybrid-x86\/6. Accessed: 2019-01-17."},{"key":"e_1_3_2_1_3_1","unstructured":"[n.d.]. PID controller - Wikipedia. https:\/\/en.wikipedia.org\/wiki\/PID_controller. Accessed: 2019-01-25.  [n.d.]. PID controller - Wikipedia. https:\/\/en.wikipedia.org\/wiki\/PID_controller. Accessed: 2019-01-25."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1023\/B:IJPP.0000004508.14594.b9"},{"volume-title":"Performance Analysis of Systems and Software, 2009. ISPASS 2009. IEEE International Symposium on. IEEE, 163\u2013174","author":"Bakhoda A.","key":"e_1_3_2_1_5_1","unstructured":"A. Bakhoda , G. Yuan , W. Fung , H. Wong , and T. Aamodt . 2009. Analyzing CUDA workloads using a detailed GPU simulator . In Performance Analysis of Systems and Software, 2009. ISPASS 2009. IEEE International Symposium on. IEEE, 163\u2013174 . A. Bakhoda, G. Yuan, W. Fung, H. Wong, and T. Aamodt. 2009. Analyzing CUDA workloads using a detailed GPU simulator. In Performance Analysis of Systems and Software, 2009. ISPASS 2009. IEEE International Symposium on. IEEE, 163\u2013174."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555792"},{"key":"e_1_3_2_1_7_1","unstructured":"Bryan Black. [n.d.]. Die Stacking Is Happening!https:\/\/www.microarch.org\/micro46\/files\/keynote1.pdf. Accessed: 2019-02-11.  Bryan Black. [n.d.]. Die Stacking Is Happening!https:\/\/www.microarch.org\/micro46\/files\/keynote1.pdf. Accessed: 2019-02-11."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/N-SSC.2007.4785534"},{"volume-title":"Workload Characterization, 2009. IISWC 2009. IEEE International Symposium on. IEEE, 188\u2013197","author":"Charles J.","key":"e_1_3_2_1_9_1","unstructured":"J. Charles , P. Jassi , N. Ananth , A. Sadat , and A. Fedorova . 2009. Evaluation of the Intel\u00ae Core\u2122 i7 Turbo Boost feature . In Workload Characterization, 2009. IISWC 2009. IEEE International Symposium on. IEEE, 188\u2013197 . J. Charles, P. Jassi, N. Ananth, A. Sadat, and A. Fedorova. 2009. Evaluation of the Intel\u00ae Core\u2122 i7 Turbo Boost feature. In Workload Characterization, 2009. IISWC 2009. IEEE International Symposium on. IEEE, 188\u2013197."},{"volume-title":"Workload Characterization, 2009. IISWC 2009. IEEE International Symposium on. Ieee, 44\u201354","author":"Che S.","key":"e_1_3_2_1_10_1","unstructured":"S. Che , M. Boyer , J. Meng , D. Tarjan , J. Sheaffer , S. Lee , and K. Skadron . 2009. Rodinia: A benchmark suite for heterogeneous computing . In Workload Characterization, 2009. IISWC 2009. IEEE International Symposium on. Ieee, 44\u201354 . S. Che, M. Boyer, J. Meng, D. Tarjan, J. Sheaffer, S. Lee, and K. Skadron. 2009. Rodinia: A benchmark suite for heterogeneous computing. In Workload Characterization, 2009. IISWC 2009. IEEE International Symposium on. Ieee, 44\u201354."},{"key":"e_1_3_2_1_11_1","volume-title":"Automation & Test in Europe Conference & Exhibition","author":"Gupta M.","year":"2007","unstructured":"M. Gupta , J. Oatley , R. Joseph , G. Wei , and D. Brooks . 2007. Understanding voltage variations in chip multiprocessors using a distributed power-delivery network. In Design , Automation & Test in Europe Conference & Exhibition , 2007 . DATE\u201907. IEEE, 1\u20136. M. Gupta, J. Oatley, R. Joseph, G. Wei, and D. Brooks. 2007. Understanding voltage variations in chip multiprocessors using a distributed power-delivery network. In Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE\u201907. IEEE, 1\u20136."},{"volume-title":"8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES-2012)","author":"Heirman W.","key":"e_1_3_2_1_12_1","unstructured":"W. Heirman , T. Carlson , and L. Eeckhout . 2012. Sniper: Scalable and accurate parallel multi-core simulation. In 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES-2012) . High-Performance and Embedded Architecture and Compilation Network of Excellence (HiPEAC), 91\u201394. W. Heirman, T. Carlson, and L. Eeckhout. 2012. Sniper: Scalable and accurate parallel multi-core simulation. In 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES-2012). High-Performance and Embedded Architecture and Compilation Network of Excellence (HiPEAC), 91\u201394."},{"volume-title":"High Performance Computer Architecture (HPCA), 2015 IEEE 21st International Symposium on. IEEE, 271\u2013282","author":"Hsu C.","key":"e_1_3_2_1_13_1","unstructured":"C. Hsu , Y. Zhang , M. Laurenzano , D. Meisner , T. Wenisch , J. Mars , L. Tang , and R. Dreslinski . 2015. Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting . In High Performance Computer Architecture (HPCA), 2015 IEEE 21st International Symposium on. IEEE, 271\u2013282 . C. Hsu, Y. Zhang, M. Laurenzano, D. Meisner, T. Wenisch, J. Mars, L. Tang, and R. Dreslinski. 2015. Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting. In High Performance Computer Architecture (HPCA), 2015 IEEE 21st International Symposium on. IEEE, 271\u2013282."},{"volume-title":"Proceedings of the 48th International Symposium on Microarchitecture. ACM, 598\u2013610","author":"Kasture H.","key":"e_1_3_2_1_14_1","unstructured":"H. Kasture , D. Bartolini , N. Beckmann , and D. Sanchez . 2015. Rubik: Fast analytical power management for latency-critical systems . In Proceedings of the 48th International Symposium on Microarchitecture. ACM, 598\u2013610 . H. Kasture, D. Bartolini, N. Beckmann, and D. Sanchez. 2015. Rubik: Fast analytical power management for latency-critical systems. In Proceedings of the 48th International Symposium on Microarchitecture. ACM, 598\u2013610."},{"volume-title":"Opportunities for Fine-Grained Adaptive Voltage Scaling to Improve System-Level Energy Efficiency. Master\u2019s thesis. EECS Department","key":"e_1_3_2_1_15_1","unstructured":"Ben Keller. 2015. Opportunities for Fine-Grained Adaptive Voltage Scaling to Improve System-Level Energy Efficiency. Master\u2019s thesis. EECS Department , University of California , Berkeley. Ben Keller. 2015. Opportunities for Fine-Grained Adaptive Voltage Scaling to Improve System-Level Energy Efficiency. Master\u2019s thesis. EECS Department, University of California, Berkeley."},{"key":"e_1_3_2_1_16_1","unstructured":"Y. Lee B. Zimmer A. Waterman A. Puggelli J. Kwak R. Jevtic B. Keller S. Bailey M. Blagojevic P. Chiu H. Cook R. Avizienis B. Richards E. Alon B. Nikolic and K. Asanovic. [n.d.]. Raven: A 28nm RISC-V Vector Processor with Integrated Switched-Capacitor DC-DC Converters and Adaptive Clocking.  Y. Lee B. Zimmer A. Waterman A. Puggelli J. Kwak R. Jevtic B. Keller S. Bailey M. Blagojevic P. Chiu H. Cook R. Avizienis B. Richards E. Alon B. Nikolic and K. Asanovic. [n.d.]. Raven: A 28nm RISC-V Vector Processor with Integrated Switched-Capacitor DC-DC Converters and Adaptive Clocking."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"crossref","unstructured":"J. Leng T. Hetherington A. ElTantawy S. Gilani N. Kim T. Aamodt and V. Reddi. 2013. GPUWattch: enabling energy optimizations in GPGPUs. In ACM SIGARCH Computer Architecture News Vol.\u00a041. ACM 487\u2013498.  J. Leng T. Hetherington A. ElTantawy S. Gilani N. Kim T. Aamodt and V. Reddi. 2013. GPUWattch: enabling energy optimizations in GPGPUs. In ACM SIGARCH Computer Architecture News Vol.\u00a041. ACM 487\u2013498.","DOI":"10.1145\/2508148.2485964"},{"volume-title":"Proceedings of the 42nd Annual IEEE\/ACM International Symposium on Microarchitecture. ACM, 469\u2013480","author":"Li S.","key":"e_1_3_2_1_18_1","unstructured":"S. Li , J. Ahn , R. Strong , J. Brockman , D. Tullsen , and N. Jouppi . 2009. McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures . In Proceedings of the 42nd Annual IEEE\/ACM International Symposium on Microarchitecture. ACM, 469\u2013480 . S. Li, J. Ahn, R. Strong, J. Brockman, D. Tullsen, and N. Jouppi. 2009. McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proceedings of the 42nd Annual IEEE\/ACM International Symposium on Microarchitecture. ACM, 469\u2013480."},{"volume-title":"ACM SIGARCH computer architecture news, Vol.\u00a036","author":"Loh G.","key":"e_1_3_2_1_19_1","unstructured":"G. Loh . 2008. 3D-stacked memory architectures for multi-core processors . In ACM SIGARCH computer architecture news, Vol.\u00a036 . IEEE Computer Society , 453\u2013464. G. Loh. 2008. 3D-stacked memory architectures for multi-core processors. In ACM SIGARCH computer architecture news, Vol.\u00a036. IEEE Computer Society, 453\u2013464."},{"volume-title":"2018 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 466\u2013479","author":"Pal S.","key":"e_1_3_2_1_20_1","unstructured":"S. Pal , D. Petrisko , A. Bajwa , P. Gupta , S. Iyer , and R. Kumar . 2018. A Case for Packageless Processors . In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 466\u2013479 . S. Pal, D. Petrisko, A. Bajwa, P. Gupta, S. Iyer, and R. Kumar. 2018. A Case for Packageless Processors. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 466\u2013479."},{"volume-title":"Proceedings of the 31st Annual ACM Symposium on Applied Computing. ACM, 1717\u20131723","author":"Park J.","key":"e_1_3_2_1_21_1","unstructured":"J. Park , C. Hsieh , N. Dutt , and S. Lim . 2016. Co-Cap: energy-efficient cooperative CPU-GPU frequency capping for mobile games . In Proceedings of the 31st Annual ACM Symposium on Applied Computing. ACM, 1717\u20131723 . J. Park, C. Hsieh, N. Dutt, and S. Lim. 2016. Co-Cap: energy-efficient cooperative CPU-GPU frequency capping for mobile games. In Proceedings of the 31st Annual ACM Symposium on Applied Computing. ACM, 1717\u20131723."},{"volume-title":"Proceedings of the 42Nd Annual International Symposium on Computer Architecture","author":"Paul I.","key":"e_1_3_2_1_22_1","unstructured":"I. Paul , W. Huang , M. Arora , and S. Yalamanchili . 2015. Harmonia: Balancing Compute and Memory Power in High-performance GPUs . In Proceedings of the 42Nd Annual International Symposium on Computer Architecture ( Portland, Oregon) (ISCA \u201915). ACM, New York, NY, USA, 54\u201365. https:\/\/doi.org\/10.1145\/2749469.2750404 10.1145\/2749469.2750404 I. Paul, W. Huang, M. Arora, and S. Yalamanchili. 2015. Harmonia: Balancing Compute and Memory Power in High-performance GPUs. In Proceedings of the 42Nd Annual International Symposium on Computer Architecture (Portland, Oregon) (ISCA \u201915). ACM, New York, NY, USA, 54\u201365. https:\/\/doi.org\/10.1145\/2749469.2750404"},{"volume-title":"Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis","author":"Paul I.","key":"e_1_3_2_1_23_1","unstructured":"I. Paul , V. Ravi , S. Manne , M. Arora , and S. Yalamanchili . 2013. Coordinated Energy Management in Heterogeneous Processors . In Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis ( Denver, Colorado) (SC \u201913). ACM, New York, NY, USA, Article 59, 12\u00a0pages. https:\/\/doi.org\/10.1145\/2503210.2503227 10.1145\/2503210.2503227 I. Paul, V. Ravi, S. Manne, M. Arora, and S. Yalamanchili. 2013. Coordinated Energy Management in Heterogeneous Processors. In Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis(Denver, Colorado) (SC \u201913). ACM, New York, NY, USA, Article 59, 12\u00a0pages. https:\/\/doi.org\/10.1145\/2503210.2503227"},{"volume-title":"Tangram: Integrated Control of Heterogeneous Computers. In Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture","author":"Pothukuchi R.","key":"e_1_3_2_1_24_1","unstructured":"R. Pothukuchi , J. Greathouse , K. Rao , C. Erb , L. Piga , P. Voulgaris , and T.2019. Tangram: Integrated Control of Heterogeneous Computers. In Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture ( Columbus, OH, USA) (MICRO \u201952). Association for Computing Machinery, New York, NY, USA, 384\u2013398. https:\/\/doi.org\/10.1145\/3352460.3358285 10.1145\/3352460.3358285 R. Pothukuchi, J. Greathouse, K. Rao, C. Erb, L. Piga, P. Voulgaris, and T.2019. Tangram: Integrated Control of Heterogeneous Computers. In Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture (Columbus, OH, USA) (MICRO \u201952). Association for Computing Machinery, New York, NY, USA, 384\u2013398. https:\/\/doi.org\/10.1145\/3352460.3358285"},{"volume-title":"Dual Channel PWM Controller with Integrated Driver for IMVP8 CPU Core Power Supply","author":"Richtek Technology Corporation","key":"e_1_3_2_1_25_1","unstructured":"Richtek Technology Corporation . 2015. Dual Channel PWM Controller with Integrated Driver for IMVP8 CPU Core Power Supply . http:\/\/www.richtek.com\/assets\/product_file\/RT3606BC\/DS3606BC-00.pdf Accessed: 2016-09-30. Richtek Technology Corporation. 2015. Dual Channel PWM Controller with Integrated Driver for IMVP8 CPU Core Power Supply. http:\/\/www.richtek.com\/assets\/product_file\/RT3606BC\/DS3606BC-00.pdf Accessed: 2016-09-30."},{"key":"e_1_3_2_1_26_1","volume-title":"Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP. In 2018 IEEE 25th International Conference on High Performance Computing (HiPC). 112\u2013122","author":"Straube K.","year":"2018","unstructured":"K. Straube , J. Lowe-Power , C. Nitta , M. Farrens , and V. Akella . 2018 . Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP. In 2018 IEEE 25th International Conference on High Performance Computing (HiPC). 112\u2013122 . https:\/\/doi.org\/10.1109\/HiPC. 2018 .00021 10.1109\/HiPC.2018.00021 K. Straube, J. Lowe-Power, C. Nitta, M. Farrens, and V. Akella. 2018. Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP. In 2018 IEEE 25th International Conference on High Performance Computing (HiPC). 112\u2013122. https:\/\/doi.org\/10.1109\/HiPC.2018.00021"},{"volume-title":"Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing. In 2017 IEEE International Conference on Computer Design (ICCD). IEEE, 649\u2013652","author":"Straube K.","key":"e_1_3_2_1_27_1","unstructured":"K. Straube , C. Nitta , R. Amirtharajah , M. Farrens , and V. Akella . 2017 . Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing. In 2017 IEEE International Conference on Computer Design (ICCD). IEEE, 649\u2013652 . K. Straube, C. Nitta, R. Amirtharajah, M. Farrens, and V. Akella. 2017. Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing. In 2017 IEEE International Conference on Computer Design (ICCD). IEEE, 649\u2013652."},{"volume-title":"ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC). IEEE, 98\u2013101","author":"Suresh V.","key":"e_1_3_2_1_28_1","unstructured":"V. Suresh , S. Satpathy , S. Mathew , M. Anders , H. Kaul , A. Agarwal , S. Hsu , and R. Krishnamurthy . 2018. A 230mV-950mV 2.8 Tbps\/W Unified SHA256\/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS . In ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC). IEEE, 98\u2013101 . V. Suresh, S. Satpathy, S. Mathew, M. Anders, H. Kaul, A. Agarwal, S. Hsu, and R. Krishnamurthy. 2018. A 230mV-950mV 2.8 Tbps\/W Unified SHA256\/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS. In ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC). IEEE, 98\u2013101."},{"volume-title":"Smart Cities and Green ICT Systems (SMARTGREENS), 2015 International Conference on. IEEE, 1\u20138.","author":"Tsuzuku K.","key":"e_1_3_2_1_29_1","unstructured":"K. Tsuzuku and T. Endo . 2015. Power capping of CPU-GPU heterogeneous systems using power and performance models . In Smart Cities and Green ICT Systems (SMARTGREENS), 2015 International Conference on. IEEE, 1\u20138. K. Tsuzuku and T. Endo. 2015. Power capping of CPU-GPU heterogeneous systems using power and performance models. In Smart Cities and Green ICT Systems (SMARTGREENS), 2015 International Conference on. IEEE, 1\u20138."}],"event":{"name":"ICPP '20: 49th International Conference on Parallel Processing","acronym":"ICPP '20","location":"Edmonton AB Canada"},"container-title":["49th International Conference on Parallel Processing - ICPP"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3404397.3404448","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3404397.3404448","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:31:42Z","timestamp":1750195902000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3404397.3404448"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8,17]]},"references-count":29,"alternative-id":["10.1145\/3404397.3404448","10.1145\/3404397"],"URL":"https:\/\/doi.org\/10.1145\/3404397.3404448","relation":{},"subject":[],"published":{"date-parts":[[2020,8,17]]},"assertion":[{"value":"2020-08-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}