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Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2020,11,30]]},"abstract":"<jats:p>\n            This article presents a novel energy-efficient cache design for massively parallel, throughput-oriented architectures like GPUs. Unlike L1 data cache on modern GPUs, L2 cache shared by all of the streaming multiprocessors is not the primary performance bottleneck, but it does consume a large amount of chip energy. We observe that L2 cache is significantly underutilized by spending 95.6% of the time storing useless data. If such \u201cdead time\u201d on L2 is identified and reduced, L2\u2019s energy efficiency can be drastically improved. Fortunately, we discover that the SIMT programming model of GPUs provides a unique feature among threads: instruction-level data locality similarity, which can be used to accurately predict the data re-reference counts at L2 cache block level. We propose a simple design that leverages this\n            <jats:italic>Lo<\/jats:italic>\n            cality\n            <jats:italic>S<\/jats:italic>\n            imilarity to build an energy-efficient GPU L2\n            <jats:italic>Cache<\/jats:italic>\n            , named\n            <jats:italic>LoSCache<\/jats:italic>\n            . Specifically, LoSCache uses the data locality information from a small group of cooperative thread arrays to dynamically predict the L2-level data re-reference counts of the remaining cooperative thread arrays. After that, specific L2 cache lines can be powered off if they are predicted to be \u201cdead\u201d after certain accesses. Experimental results on a wide range of applications demonstrate that our proposed design can significantly reduce the L2 cache energy by an average of 64% with only 0.5% performance loss. In addition, LoSCache is cost effective, independent of the scheduling policies, and compatible with the state-of-the-art L1 cache designs for additional energy savings.\n          <\/jats:p>","DOI":"10.1145\/3408060","type":"journal-article","created":{"date-parts":[[2020,8,18]],"date-time":"2020-08-18T16:54:09Z","timestamp":1597769649000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Energy-Efficient GPU L2 Cache Design Using Instruction-Level Data Locality Similarity"],"prefix":"10.1145","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8256-7585","authenticated-orcid":false,"given":"Jingweijia","family":"Tan","sequence":"first","affiliation":[{"name":"Jilin University, Jilin, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kaige","family":"Yan","sequence":"additional","affiliation":[{"name":"Jilin University, Jilin, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuaiwen Leon","family":"Song","sequence":"additional","affiliation":[{"name":"Pacific Northwest National Laboratory, Richland, WA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xin","family":"Fu","sequence":"additional","affiliation":[{"name":"University of Houston, Houston, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,8,18]]},"reference":[{"volume-title":"n.d. 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