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Mapping and scheduling of these applications are critical for system performance and energy consumption, especially in Network-on-Chip\u2013 (NoC) based multicore systems. These systems with multitasking processors offer a better opportunity for parallel application execution. Mapping solutions generated at design time may be inappropriate for dynamic workloads. To improve the utilization of the underlying multicore platform and cope with the dynamism of application workload, often task allocation is carried out dynamically. This article presents a hybrid task allocation and scheduling strategy that exploits the design-time results at runtime. By considering the multitasking capability of the processors, communication energy, and timing characteristics of the tasks, different allocation options are obtained at design time. During runtime, based on the availability of the platform resources and application requirements, the design-time allocations are adapted for mapping and scheduling of tasks, which result in improved runtime performance. Experimental results demonstrate that the proposed approach achieves an on average 11.5%, 22.3%, 28.6%, and 34.6% reduction in communication energy consumption as compared to CAM [18], DEAMS [4], TSMM [38], and CPNN [32], respectively, for NoC-based multicore platforms with multitasking processors. Also, the deadline satisfaction of the tasks of allocated applications improves on an average by 32.8% when compared with the state-of-the-art dynamic resource allocation approaches.<\/jats:p>","DOI":"10.1145\/3408324","type":"journal-article","created":{"date-parts":[[2020,12,7]],"date-time":"2020-12-07T18:26:48Z","timestamp":1607365608000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Adaptive Task Allocation and Scheduling on NoC-based Multicore Platforms with Multitasking Processors"],"prefix":"10.1145","volume":"20","author":[{"given":"Suraj","family":"Paul","sequence":"first","affiliation":[{"name":"Indian Institute of Engineering Science and Technology, Shibpur, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Navonil","family":"Chatterjee","sequence":"additional","affiliation":[{"name":"Universit\u00e9 Bretagne Sud, Lab-STICC, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4226-9043","authenticated-orcid":false,"given":"Prasun","family":"Ghosal","sequence":"additional","affiliation":[{"name":"Indian Institute of Engineering Science and Technology, Shibpur, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean-Philippe","family":"Diguet","sequence":"additional","affiliation":[{"name":"CNRS, Lab-STICC, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,12,7]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.106"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2953878"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/3055512"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2017.01.008"},{"key":"e_1_2_1_5_1","first-page":"1","article-title":"Run-time task allocation considering user behavior in embedded multiprocessor networks-on-chip","volume":"29","author":"Chou C.","year":"2010","unstructured":"C. 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