{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:23:20Z","timestamp":1750220600296,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":4,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,9,30]],"date-time":"2020-09-30T00:00:00Z","timestamp":1601424000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,9,30]]},"DOI":"10.1145\/3410463.3414662","type":"proceedings-article","created":{"date-parts":[[2020,9,30]],"date-time":"2020-09-30T10:43:04Z","timestamp":1601462584000},"page":"155-156","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Decoupled Address Translation for Heterogeneous Memory Systems"],"prefix":"10.1145","author":[{"given":"Bokyeong","family":"Kim","sequence":"first","affiliation":[{"name":"Samsung Research, Seoul, Republic of Korea"}]},{"given":"Soojin","family":"Hwang","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Republic of Korea"}]},{"given":"Sanghoon","family":"Cha","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Republic of Korea"}]},{"given":"Chang Hyun","family":"Park","sequence":"additional","affiliation":[{"name":"Uppsala University, Uppsala, Sweden"}]},{"given":"Jongse","family":"Park","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Republic of Korea"}]},{"given":"Jaehyuk","family":"Huh","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Republic of Korea"}]}],"member":"320","published-online":{"date-parts":[[2020,9,30]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Qureshi","author":"Chou Chiachen","year":"2014","unstructured":"Chiachen Chou , Aamer Jaleel , and Moinuddin K . Qureshi . 2014 . CAMEO : A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache. In Proceedings of the 2014 47th Annual IEEE\/ACM International Symposium on Microarchitecture. 1--12. Chiachen Chou, Aamer Jaleel, and Moinuddin K. Qureshi. 2014. CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache. In Proceedings of the 2014 47th Annual IEEE\/ACM International Symposium on Microarchitecture. 1--12."},{"volume-title":"Proceedings of the 2015 21st Annual IEEE\/ACM International Symposium on High Performance Computer Architecture. 126--136","author":"Meswani M. R.","key":"e_1_3_2_1_2_1","unstructured":"M. R. Meswani , S. Blagodurov , D. Roberts , J. Slice , M. Ignatowski , and G. H. Loh . 2015. Heterogeneous memory architectures: A HW\/SW approach for mixing die-stacked and off-package memories . In Proceedings of the 2015 21st Annual IEEE\/ACM International Symposium on High Performance Computer Architecture. 126--136 . M. R. Meswani, S. Blagodurov, D. Roberts, J. Slice, M. Ignatowski, and G. H. Loh. 2015. Heterogeneous memory architectures: A HW\/SW approach for mixing die-stacked and off-package memories. In Proceedings of the 2015 21st Annual IEEE\/ACM International Symposium on High Performance Computer Architecture. 126--136."},{"key":"e_1_3_2_1_3_1","volume":"201","author":"Park C. H.","unstructured":"C. H. Park , T. Heo , J. Jeong , and J. Huh. 201 7. Hybrid TLB coalescing: Improving TLB translation coverage under diverse fragmented memory allocations. In Proceedings of the 2017 44th Annual IEEE\/ACM International Symposium on Computer Architecture. 444--456. C. H. Park, T. Heo, J. Jeong, and J. Huh. 2017. Hybrid TLB coalescing: Improving TLB translation coverage under diverse fragmented memory allocations. In Proceedings of the 2017 44th Annual IEEE\/ACM International Symposium on Computer Architecture. 444--456.","journal-title":"J. Huh."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.56"}],"event":{"name":"PACT '20: International Conference on Parallel Architectures and Compilation Techniques","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Virtual Event GA USA","acronym":"PACT '20"},"container-title":["Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3410463.3414662","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3410463.3414662","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:31:58Z","timestamp":1750195918000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3410463.3414662"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,30]]},"references-count":4,"alternative-id":["10.1145\/3410463.3414662","10.1145\/3410463"],"URL":"https:\/\/doi.org\/10.1145\/3410463.3414662","relation":{},"subject":[],"published":{"date-parts":[[2020,9,30]]},"assertion":[{"value":"2020-09-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}