{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:23:20Z","timestamp":1750220600232,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":6,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,9,30]],"date-time":"2020-09-30T00:00:00Z","timestamp":1601424000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Science Foundation of China","award":["61872201"],"award-info":[{"award-number":["61872201"]}]},{"name":"Natural Science Foundation of Tianjin City","award":["18ZXZNGX00200","18JCYBJC15600","18ZXZNGX00140"],"award-info":[{"award-number":["18ZXZNGX00200","18JCYBJC15600","18ZXZNGX00140"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,9,30]]},"DOI":"10.1145\/3410463.3414668","type":"proceedings-article","created":{"date-parts":[[2020,9,30]],"date-time":"2020-09-30T10:43:04Z","timestamp":1601462584000},"page":"153-154","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Deep Learning Assisted Resource Partitioning for Improving Performance on Commodity Servers"],"prefix":"10.1145","author":[{"given":"Ruobing","family":"Chen","sequence":"first","affiliation":[{"name":"Nankai University, Tianjin, China"}]},{"given":"Jinping","family":"Wu","sequence":"additional","affiliation":[{"name":"Nankai University, Tianjin, China"}]},{"given":"Haosen","family":"Shi","sequence":"additional","affiliation":[{"name":"Nankai University, Tianjin, China"}]},{"given":"Yusen","family":"Li","sequence":"additional","affiliation":[{"name":"Nankai University, Tianjin, China"}]},{"given":"Haiyan","family":"Yin","sequence":"additional","affiliation":[{"name":"Nanyang Technological University, Singapore, Singapore"}]},{"given":"Shanjiang","family":"Tang","sequence":"additional","affiliation":[{"name":"Tianjin University, Tianjin, China"}]},{"given":"Xiaoguang","family":"Liu","sequence":"additional","affiliation":[{"name":"Nankai University, Tianjin, China"}]},{"given":"Gang","family":"Wang","sequence":"additional","affiliation":[{"name":"Nankai University, Tianjin, China"}]}],"member":"320","published-online":{"date-parts":[[2020,9,30]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"H. Andrew Khawar M Abbasi and C. Marcel. 2019. Introduction to Memory Bandwidth Allocation. https:\/\/software.intel.com\/en-us\/articles\/introduction-to-memory-bandwidth-allocation.  H. Andrew Khawar M Abbasi and C. Marcel. 2019. Introduction to Memory Bandwidth Allocation. https:\/\/software.intel.com\/en-us\/articles\/introduction-to-memory-bandwidth-allocation."},{"volume-title":"KPart: A Hybrid Cache Partitioning-Sharing Technique for Commodity Multicores. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA). 104--117","author":"El-Sayed N.","key":"e_1_3_2_1_2_1"},{"key":"e_1_3_2_1_3_1","unstructured":"CAT GUIDE. 2019. Introduction to Cache Allocation Technology in the Intel\u00ae Xeon\u00ae Processor E5 v4 Family. https:\/\/software.intel.com\/en-us\/articles\/introduction-to-cache-allocation-technology\/.  CAT GUIDE. 2019. Introduction to Cache Allocation Technology in the Intel\u00ae Xeon\u00ae Processor E5 v4 Family. https:\/\/software.intel.com\/en-us\/articles\/introduction-to-cache-allocation-technology\/."},{"volume-title":"SPEC2017:Standard Performance Evaluation Corporation. https:\/\/www.spec.org\/cpu2017\/.","year":"2017","author":"SPEC","key":"e_1_3_2_1_4_1"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3190508.3190511"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/3337821.3337863"}],"event":{"name":"PACT '20: International Conference on Parallel Architectures and Compilation Techniques","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Virtual Event GA USA","acronym":"PACT '20"},"container-title":["Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3410463.3414668","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3410463.3414668","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:31:58Z","timestamp":1750195918000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3410463.3414668"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,30]]},"references-count":6,"alternative-id":["10.1145\/3410463.3414668","10.1145\/3410463"],"URL":"https:\/\/doi.org\/10.1145\/3410463.3414668","relation":{},"subject":[],"published":{"date-parts":[[2020,9,30]]},"assertion":[{"value":"2020-09-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}