{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,4]],"date-time":"2025-09-04T14:34:52Z","timestamp":1756996492182,"version":"3.41.0"},"reference-count":17,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2020,7,27]],"date-time":"2020-07-27T00:00:00Z","timestamp":1595808000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGBED Rev."],"published-print":{"date-parts":[[2020,7,27]]},"abstract":"<jats:p>\n            In a quest for making FPGA technology more accessible to the software community, Xilinx recently released PYNQ, a framework for Zynq that relies on Python and\n            <jats:italic>overlays<\/jats:italic>\n            to ease the integration of functionalities of the programmable logic into applications. In this work we build upon this framework to enable transparent hardware acceleration for scientific computations for Zynq. We do so by providing a custom NumPy library designed for PYNQ, as it is the de-facto scientific library for Python. We then demonstrate the effectiveness of the proposed approach on a biomedical use case involving the extraction of features from the Electroencephalography (EEG).\n          <\/jats:p>","DOI":"10.1145\/3412821.3412826","type":"journal-article","created":{"date-parts":[[2020,7,27]],"date-time":"2020-07-27T15:58:23Z","timestamp":1595865503000},"page":"30-35","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Enabling transparent hardware acceleration on Zynq SoC for scientific computing"],"prefix":"10.1145","volume":"17","author":[{"given":"Luca","family":"Stornaiuolo","sequence":"first","affiliation":[{"name":"Politecnico di Milano, Milan, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Filippo","family":"Carloni","sequence":"additional","affiliation":[{"name":"Politecnico di Milano, Milan, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Riccardo","family":"Pressiani","sequence":"additional","affiliation":[{"name":"Politecnico di Milano, Milan, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giuseppe","family":"Natale","sequence":"additional","affiliation":[{"name":"Politecnico di Milano, Milan, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marco","family":"Santambrogio","sequence":"additional","affiliation":[{"name":"Politecnico di Milano, Milan, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donatella","family":"Sciuto","sequence":"additional","affiliation":[{"name":"Politecnico di Milano, Milan, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,7,27]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"2014 ACM\/IEEE 41st International Symposium on, IEEE","author":"Putnam A.","year":"2014","unstructured":"A. Putnam , A. M. Caulfield , E. S. Chung , D. Chiou , K. Constantinides , J. Demme , H. Esmaeilzadeh , J. Fowers , G. P. Gopal , J. Gray , reconfigurable fabric for accelerating large-scale datacenter services,\" in Computer Architecture (ISCA) , 2014 ACM\/IEEE 41st International Symposium on, IEEE , 2014 . A. Putnam, A. M. Caulfield, E. S. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, G. P. Gopal, J. Gray, et al., \"A reconfigurable fabric for accelerating large-scale datacenter services,\" in Computer Architecture (ISCA), 2014 ACM\/IEEE 41st International Symposium on, IEEE, 2014."},{"key":"e_1_2_1_2_1","volume-title":"The 2017 Top Programming Languages.\" https:\/\/spectrum.ieee.org\/computing\/software\/the-2017-top-programming-languages (accessed: 5th of","author":"Spectrum IEEE","year":"2017","unstructured":"\" IEEE Spectrum : The 2017 Top Programming Languages.\" https:\/\/spectrum.ieee.org\/computing\/software\/the-2017-top-programming-languages (accessed: 5th of October 2017 ). \"IEEE Spectrum: The 2017 Top Programming Languages.\" https:\/\/spectrum.ieee.org\/computing\/software\/the-2017-top-programming-languages (accessed: 5th of October 2017)."},{"key":"e_1_2_1_3_1","first-page":"132","volume-title":"Fpga-based embedded system implementation of audio signal alignment,\" in 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","author":"Stornaiuolo L.","year":"2019","unstructured":"L. Stornaiuolo , M. Perini , M. D. Santambrogio , and D. Sciuto , \" Fpga-based embedded system implementation of audio signal alignment,\" in 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) , pp. 132 -- 139 , IEEE , 2019 . L. Stornaiuolo, M. Perini, M. D. Santambrogio, and D. Sciuto, \"Fpga-based embedded system implementation of audio signal alignment,\" in 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 132--139, IEEE, 2019."},{"key":"e_1_2_1_4_1","volume-title":"FCCM '17","author":"Schmidt A. G.","year":"2017","unstructured":"A. G. Schmidt , G. Weisz , and M. French , \" Evaluating Rapid Application Development with Python for Heterogeneous Processor-based FPGAs,\" in Proceedings of the 25th International Symposium on Field-Programmable Custom Computing Machines , FCCM '17 , IEEE, 2017 . A. G. Schmidt, G. Weisz, and M. French, \"Evaluating Rapid Application Development with Python for Heterogeneous Processor-based FPGAs,\" in Proceedings of the 25th International Symposium on Field-Programmable Custom Computing Machines, FCCM '17, IEEE, 2017."},{"key":"e_1_2_1_5_1","volume-title":"2017 27th International Conference on, IEEE","author":"Jan\u00dfen B.","year":"2017","unstructured":"B. Jan\u00dfen , P. Zimprich , and M. H\u00fcbner , \" A dynamic partial reconfigurable overlay concept for PYNQ,\" in Field Programmable Logic and Applications (FPL) , 2017 27th International Conference on, IEEE , 2017 . B. Jan\u00dfen, P. Zimprich, and M. H\u00fcbner, \"A dynamic partial reconfigurable overlay concept for PYNQ,\" in Field Programmable Logic and Applications (FPL), 2017 27th International Conference on, IEEE, 2017."},{"key":"e_1_2_1_6_1","volume-title":"2017 6th International Conference on, IEEE","author":"Koromilas E.","year":"2017","unstructured":"E. Koromilas , I. Stamelos , C. Kachris , and D. Soudris , \" Spark acceleration on FPGAs: A use case on machine learning in Pynq,\" in Modern Circuits and Systems Technologies (MOCAST) , 2017 6th International Conference on, IEEE , 2017 . E. Koromilas, I. Stamelos, C. Kachris, and D. Soudris, \"Spark acceleration on FPGAs: A use case on machine learning in Pynq,\" in Modern Circuits and Systems Technologies (MOCAST), 2017 6th International Conference on, IEEE, 2017."},{"key":"e_1_2_1_7_1","volume-title":"Transparent GPU execution of NumPy applications,\" in Parallel & Distributed Processing Symposium Workshops (IPDPSW)","author":"Blum T.","year":"2014","unstructured":"T. Blum , M. R. Kristensen , and B. Vinter , \" Transparent GPU execution of NumPy applications,\" in Parallel & Distributed Processing Symposium Workshops (IPDPSW) , 2014 IEEE International , IEEE , 2014. T. Blum, M. R. Kristensen, and B. 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Tai, \"PyHDL: Hardware Scripting with Python,\" in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2003."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2560032"},{"key":"e_1_2_1_12_1","volume-title":"Predictive runtime code scheduling for heterogeneous architectures.,\" HiPEAC","author":"Jim\u00e9nez V. J.","year":"2009","unstructured":"V. J. Jim\u00e9nez , L. Vilanova , I. Gelado , M. Gil , G. Fursin , and N. Navarro , \" Predictive runtime code scheduling for heterogeneous architectures.,\" HiPEAC , vol. 9 , 2009 . V. J. Jim\u00e9nez, L. Vilanova, I. Gelado, M. Gil, G. Fursin, and N. Navarro, \"Predictive runtime code scheduling for heterogeneous architectures.,\" HiPEAC, vol. 9, 2009."},{"key":"e_1_2_1_13_1","volume-title":"January","author":"Bagni D.","year":"2016","unstructured":"D. Bagni , A. Di Fresco , J. Noguera , and F. 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Nam, \"A systematic review of hybrid brain-computer interfaces: Taxonomy and usability perspectives,\" PloS one, vol. 12, no. 4, 2017."},{"key":"e_1_2_1_15_1","volume-title":"Mne software for processing meg and eeg data,\" NeuroImage","author":"Gramfort A.","year":"2014","unstructured":"A. Gramfort , M. Luessi , E. Larson , D. A. Engemann , D. Strohmeier , C. Brodbeck , L. Parkkonen , and M. S. H\u00e4m\u00e4l\u00e4inen , \" Mne software for processing meg and eeg data,\" NeuroImage , vol. 86 , no. Supplement C , 2014 . A. Gramfort, M. Luessi, E. Larson, D. A. Engemann, D. Strohmeier, C. Brodbeck, L. Parkkonen, and M. S. H\u00e4m\u00e4l\u00e4inen, \"Mne software for processing meg and eeg data,\" NeuroImage, vol. 86, no. Supplement C, 2014."},{"issue":"3","key":"e_1_2_1_16_1","volume":"14","author":"Olejarczyk E.","year":"2017","unstructured":"E. Olejarczyk , L. Marzetti , V. Pizzella , and F. Zappasodi , \"Comparison of connectivity analyses for resting state eeg data,\" Journal of Neural Engineering , vol. 14 , no. 3 , 2017 . E. Olejarczyk, L. Marzetti, V. Pizzella, and F. Zappasodi, \"Comparison of connectivity analyses for resting state eeg data,\" Journal of Neural Engineering, vol. 14, no. 3, 2017.","journal-title":"\"Comparison of connectivity analyses for resting state eeg data,\" Journal of Neural Engineering"},{"key":"e_1_2_1_17_1","volume-title":"Boosting bit rates in noninvasive eeg single-trial classifications by feature combination and multiclass paradigms,\" IEEE Transactions on Biomedical Engineering","author":"Dornhege G.","year":"2004","unstructured":"G. Dornhege , B. Blankertz , G. Curio , and K. R. Muller , \" Boosting bit rates in noninvasive eeg single-trial classifications by feature combination and multiclass paradigms,\" IEEE Transactions on Biomedical Engineering , vol. 51 , June 2004 . G. Dornhege, B. Blankertz, G. Curio, and K. R. Muller, \"Boosting bit rates in noninvasive eeg single-trial classifications by feature combination and multiclass paradigms,\" IEEE Transactions on Biomedical Engineering, vol. 51, June 2004."}],"container-title":["ACM SIGBED Review"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3412821.3412826","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3412821.3412826","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:25:02Z","timestamp":1750195502000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3412821.3412826"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,7,27]]},"references-count":17,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2020,7,27]]}},"alternative-id":["10.1145\/3412821.3412826"],"URL":"https:\/\/doi.org\/10.1145\/3412821.3412826","relation":{},"ISSN":["1551-3688"],"issn-type":[{"type":"electronic","value":"1551-3688"}],"subject":[],"published":{"date-parts":[[2020,7,27]]},"assertion":[{"value":"2020-07-27","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}