{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:37:45Z","timestamp":1772725065765,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":34,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,11,5]],"date-time":"2020-11-05T00:00:00Z","timestamp":1604534400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,11,5]]},"DOI":"10.1145\/3414622.3431906","type":"proceedings-article","created":{"date-parts":[[2020,12,14]],"date-time":"2020-12-14T21:50:00Z","timestamp":1607982600000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Pathfinding for 2.5D interconnect technologies"],"prefix":"10.1145","author":[{"given":"Saptadeep","family":"Pal","sequence":"first","affiliation":[{"name":"University of California, Los Angeles"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Puneet","family":"Gupta","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,12,14]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2019. Heterogeneous integration roadmap 2019 edition. https:\/\/eps.ieee.org\/technology\/heterogeneous-integration-roadmap\/2019-edition.html.  2019. Heterogeneous integration roadmap 2019 edition. https:\/\/eps.ieee.org\/technology\/heterogeneous-integration-roadmap\/2019-edition.html."},{"key":"e_1_3_2_1_2_1","unstructured":"2020. 2.5D Interposer(I-Cube\u2122) Development. samsungfoundry.com.  2020. 2.5D Interposer(I-Cube \u2122 ) Development. samsungfoundry.com."},{"key":"e_1_3_2_1_3_1","unstructured":"2020. HSPICE. online. https:\/\/www.synopsys.com\/verification\/ams-verification\/hspice.html  2020. HSPICE. online. https:\/\/www.synopsys.com\/verification\/ams-verification\/hspice.html"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/16.121703"},{"key":"e_1_3_2_1_5_1","unstructured":"ESD Association et al. 2007. ESD Association Standard for the Development of an Electrostatic Discharge Control Program for-Protection of Electrical and Electronic Parts Assemblies and Equipment (excluding Electrically Initiated Explosive Devices). ANSI\/ESD S20: 20-2007. (2007).  ESD Association et al. 2007. ESD Association Standard for the Development of an Electrostatic Discharge Control Program for-Protection of Electrical and Electronic Parts Assemblies and Equipment (excluding Electrically Initiated Explosive Devices). ANSI\/ESD S20: 20-2007. (2007)."},{"key":"e_1_3_2_1_6_1","volume-title":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC). 1276--1284","author":"Bajwa A. A.","unstructured":"A. A. Bajwa , S. Jangam , S. Pal , N. Marathe , T. Bai , T. Fukushima , M. Goorsky , and S. S. Iyer . 2017. Heterogeneous Integration at Fine Pitch (10 μm) Using Thermal Compression Bonding . In 2017 IEEE 67th Electronic Components and Technology Conference (ECTC). 1276--1284 . A. A. Bajwa, S. Jangam, S. Pal, N. Marathe, T. Bai, T. Fukushima, M. Goorsky, and S. S. Iyer. 2017. Heterogeneous Integration at Fine Pitch (10 μm) Using Thermal Compression Bonding. In 2017 IEEE 67th Electronic Components and Technology Conference (ECTC). 1276--1284."},{"key":"e_1_3_2_1_7_1","volume-title":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC). 1926--1930","author":"Bajwa A. A.","unstructured":"A. A. Bajwa , S. Jangam , S. Pal , B. Vaisband , R. Irwin , M. Goorsky , and S. S. Iyer . 2018. Demonstration of a Heterogeneously Integrated System-on-Wafer (SoW) Assembly . In 2018 IEEE 68th Electronic Components and Technology Conference (ECTC). 1926--1930 . A. A. Bajwa, S. Jangam, S. Pal, B. Vaisband, R. Irwin, M. Goorsky, and S. S. Iyer. 2018. Demonstration of a Heterogeneously Integrated System-on-Wafer (SoW) Assembly. In 2018 IEEE 68th Electronic Components and Technology Conference (ECTC). 1926--1930."},{"key":"e_1_3_2_1_8_1","volume-title":"2018 IEEE International Solid - State Circuits Conference - (ISSCC). 40--42","author":"Beck N.","unstructured":"N. Beck , S. White , M. Paraschou , and S. Naffziger . 2018. 'Zeppelin': An SoC for multichip architectures . In 2018 IEEE International Solid - State Circuits Conference - (ISSCC). 40--42 . N. Beck, S. White, M. Paraschou, and S. Naffziger. 2018. 'Zeppelin': An SoC for multichip architectures. In 2018 IEEE International Solid - State Circuits Conference - (ISSCC). 40--42."},{"key":"e_1_3_2_1_9_1","volume-title":"2013 IEEE 63rd Electronic Components and Technology Conference. 852--859","author":"Chuang Y.","unstructured":"Y. Chuang , C. Yuan , J. Chen , C. Chen , C. Yang , W. Changchien , C. C. C. Liu , and F. Lee . 2013. Unified methodology for heterogeneous integration with CoWoS technology . In 2013 IEEE 63rd Electronic Components and Technology Conference. 852--859 . Y. Chuang, C. Yuan, J. Chen, C. Chen, C. Yang, W. Changchien, C. C. C. Liu, and F. Lee. 2013. Unified methodology for heterogeneous integration with CoWoS technology. In 2013 IEEE 63rd Electronic Components and Technology Conference. 852--859."},{"key":"e_1_3_2_1_10_1","unstructured":"DARPA. 2020. Common Heterogeneous Integration and IP Reuse Strategies (CHIPS).  DARPA. 2020. Common Heterogeneous Integration and IP Reuse Strategies (CHIPS)."},{"key":"e_1_3_2_1_11_1","unstructured":"Pete Ehrett Vidushi Goyal Opeoluwa Matthews Reetuparna Das Todd Austin and Valeria Bertacco. [n.d.]. Analysis of microbump overheads for 2.5 d disintegrated design. ([n. d.]).  Pete Ehrett Vidushi Goyal Opeoluwa Matthews Reetuparna Das Todd Austin and Valeria Bertacco. [n.d.]. Analysis of microbump overheads for 2.5 d disintegrated design. ([n. d.])."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2737644"},{"key":"e_1_3_2_1_13_1","unstructured":"Intel. [n.d.]. Accelerating Innovation Through A Standard Chiplet Interface: The Advanced Interface Bus (AIB).  Intel. [n.d.]. Accelerating Innovation Through A Standard Chiplet Interface: The Advanced Interface Bus (AIB)."},{"key":"e_1_3_2_1_14_1","volume-title":"Electrical Characterization of High Performance Fine Pitch Interconnects in Silicon-Interconnect Fabric. In 2018 IEEE 68th Electronic Components and Technology Conference (ECTC). 1283--1288","author":"Jangam S.","unstructured":"S. Jangam , A. A. Bajwa , K. K. Thankkappan , P. Kittur , and S. S. Iyer . 2018 . Electrical Characterization of High Performance Fine Pitch Interconnects in Silicon-Interconnect Fabric. In 2018 IEEE 68th Electronic Components and Technology Conference (ECTC). 1283--1288 . S. Jangam, A. A. Bajwa, K. K. Thankkappan, P. Kittur, and S. S. Iyer. 2018. Electrical Characterization of High Performance Fine Pitch Interconnects in Silicon-Interconnect Fabric. In 2018 IEEE 68th Electronic Components and Technology Conference (ECTC). 1283--1288."},{"key":"e_1_3_2_1_15_1","first-page":"334","article-title":"Protective seal ring for preventing die-saw induced stress","volume":"8","author":"Chen Hsien-Wei","year":"2012","unstructured":"Shin-puu Jeng, Hsien-Wei Chen , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy NF Wu , and Yu-Wen Liu . 2012 . Protective seal ring for preventing die-saw induced stress . US Patent 8 , 334 ,582. Shin-puu Jeng, Hsien-Wei Chen, Shang-Yun Hou, Hao-Yi Tsai, Anbiarshy NF Wu, and Yu-Wen Liu. 2012. Protective seal ring for preventing die-saw induced stress. US Patent 8,334,582.","journal-title":"US Patent"},{"key":"e_1_3_2_1_16_1","volume-title":"2013 IEEE 63rd Electronic Components and Technology Conference. 860--866","author":"Karim M. A.","unstructured":"M. A. Karim , P. D. Franzon , and A. Kumar . 2013. Power comparison of 2D, 3D and 2.5D interconnect solutions and power optimization of interposer interconnects . In 2013 IEEE 63rd Electronic Components and Technology Conference. 860--866 . M. A. Karim, P. D. Franzon, and A. Kumar. 2013. Power comparison of 2D, 3D and 2.5D interconnect solutions and power optimization of interposer interconnects. In 2013 IEEE 63rd Electronic Components and Technology Conference. 860--866."},{"key":"e_1_3_2_1_17_1","volume-title":"2011 IEEE 61st Electronic Components and Technology Conference (ECTC). 1160--1167","author":"Kim N.","unstructured":"N. Kim , D. Wu , D. Kim , A. Rahman , and P. Wu . 2011. Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV) . In 2011 IEEE 61st Electronic Components and Technology Conference (ECTC). 1160--1167 . N. Kim, D. Wu, D. Kim, A. Rahman, and P. Wu. 2011. Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV). In 2011 IEEE 61st Electronic Components and Technology Conference (ECTC). 1160--1167."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"crossref","unstructured":"Thierry Lazerand and David Lishan. 2014. Wafer Dicing Using Dry Etching on Standard Tapes and Frames.  Thierry Lazerand and David Lishan. 2014. Wafer Dicing Using Dry Etching on Standard Tapes and Frames.","DOI":"10.4071\/isom-TA56"},{"key":"e_1_3_2_1_19_1","unstructured":"John Lee and Mike Kelly. 2018. Amkor's 2.5D Package and HDFO - Advanced Heterogeneous Packaging Solutions. China Integrated Circuits.  John Lee and Mike Kelly. 2018. Amkor's 2.5D Package and HDFO - Advanced Heterogeneous Packaging Solutions. China Integrated Circuits."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1116\/1.3700230"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479039"},{"key":"e_1_3_2_1_22_1","volume-title":"High Bandwidth Packaging Interconnect. In 2016 IEEE 66th Electronic Components and Technology Conference (ECTC). 557--565","author":"Mahajan R.","unstructured":"R. Mahajan , R. Sankman , N. Patel , D. Kim , K. Aygun , Z. Qian , Y. Mekonnen , I. Salama , S. Sharan , D. Iyengar , and D. Mallik . 2016. Embedded Multi-die Interconnect Bridge (EMIB) - A High Density , High Bandwidth Packaging Interconnect. In 2016 IEEE 66th Electronic Components and Technology Conference (ECTC). 557--565 . R. Mahajan, R. Sankman, N. Patel, D. Kim, K. Aygun, Z. Qian, Y. Mekonnen, I. Salama, S. Sharan, D. Iyengar, and D. Mallik. 2016. Embedded Multi-die Interconnect Bridge (EMIB) - A High Density, High Bandwidth Packaging Interconnect. In 2016 IEEE 66th Electronic Components and Technology Conference (ECTC). 557--565."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2000.853403"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124545"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.2968904"},{"key":"e_1_3_2_1_26_1","volume-title":"2016 6th Electronic System-Integration Technology Conference (ESTC). 1--6.","author":"Pantano N.","unstructured":"N. Pantano , C. R. Neve , G. Van der Plas, M. Detalle, M. Verhelst, M. Heyns, and E. Beyne. 2016. Technology optimization for high bandwidth density applications on 3D interposer . In 2016 6th Electronic System-Integration Technology Conference (ESTC). 1--6. N. Pantano, C. R. Neve, G. Van der Plas, M. Detalle, M. Verhelst, M. Heyns, and E. Beyne. 2016. Technology optimization for high bandwidth density applications on 3D interposer. In 2016 6th Electronic System-Integration Technology Conference (ESTC). 1--6."},{"key":"e_1_3_2_1_27_1","unstructured":"Next Platform. 2018. Building Bigger Faster GPU Clusters using NVSwitches.  Next Platform. 2018. Building Bigger Faster GPU Clusters using NVSwitches."},{"key":"e_1_3_2_1_28_1","volume-title":"Retrieved","author":"Project Open Compute","year":"2020","unstructured":"Open Compute Project . 2020 . OCP Open Domain-Specific Architecture Sub-Project . Retrieved Nov, 2020 from https:\/\/www.opencompute.org\/wiki\/Server\/ODSA#Project_Leadership Open Compute Project. 2020. OCP Open Domain-Specific Architecture Sub-Project. Retrieved Nov, 2020 from https:\/\/www.opencompute.org\/wiki\/Server\/ODSA#Project_Leadership"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2016.7936172"},{"key":"e_1_3_2_1_30_1","volume-title":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC). 2019--2024","author":"Sa Y.","unstructured":"Y. Sa , S. Yoo , Y. Shin , M. Han , and C. Lee . 2010. Joint properties of solder capped copper pillars for 3D packaging . In 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC). 2019--2024 . Y. Sa, S. Yoo, Y. Shin, M. Han, and C. Lee. 2010. Joint properties of solder capped copper pillars for 3D packaging. In 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC). 2019--2024."},{"key":"e_1_3_2_1_31_1","volume-title":"2015 IEEE 65th Electronic Components and Technology Conference (ECTC). 1725--1729","author":"Shan L.","unstructured":"L. Shan , Y. Kwark , C. Baks , M. Gaynes , T. Chainer , M. Kapfhammer , H. Saiki , A. Kuhara , G. Aguiar , N. Ban , and Y. Nukaya . 2015. Organic Multi-Chip Module for high performance systems . In 2015 IEEE 65th Electronic Components and Technology Conference (ECTC). 1725--1729 . L. Shan, Y. Kwark, C. Baks, M. Gaynes, T. Chainer, M. Kapfhammer, H. Saiki, A. Kuhara, G. Aguiar, N. Ban, and Y. Nukaya. 2015. Organic Multi-Chip Module for high performance systems. In 2015 IEEE 65th Electronic Components and Technology Conference (ECTC). 1725--1729."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/66.827350"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.5555\/1502399"},{"key":"e_1_3_2_1_34_1","volume-title":"2018 IEEE Custom Integrated Circuits Conference (CICC). 1--8.","author":"Turner W. J.","unstructured":"W. J. Turner , J. W. Poulton , J. M. Wilson , X. Chen , S. G. Tell , M. Fojtik , T. H. Greer , B. Zimmer , S. Song , N. Nedovic , S. S. Kudva , S. R. Sudhakaran , R. Bashirullah , W. Zhao , W. J. Dally , and C. T. Gray . 2018. Ground-referenced signaling for intrachip and short-reach chip-to-chip interconnects . In 2018 IEEE Custom Integrated Circuits Conference (CICC). 1--8. W. J. Turner, J. W. Poulton, J. M. Wilson, X. Chen, S. G. Tell, M. Fojtik, T. H. Greer, B. Zimmer, S. Song, N. Nedovic, S. S. Kudva, S. R. Sudhakaran, R. Bashirullah, W. Zhao, W. J. Dally, and C. T. Gray. 2018. Ground-referenced signaling for intrachip and short-reach chip-to-chip interconnects. In 2018 IEEE Custom Integrated Circuits Conference (CICC). 1--8."}],"event":{"name":"SLIP '20: System-Level Interconnect - Problems and Pathfinding Workshop","location":"San Diego California","acronym":"SLIP '20","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CS"]},"container-title":["Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3414622.3431906","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3414622.3431906","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:03:13Z","timestamp":1750197793000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3414622.3431906"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,5]]},"references-count":34,"alternative-id":["10.1145\/3414622.3431906","10.1145\/3414622"],"URL":"https:\/\/doi.org\/10.1145\/3414622.3431906","relation":{},"subject":[],"published":{"date-parts":[[2020,11,5]]},"assertion":[{"value":"2020-12-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}