{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T12:31:45Z","timestamp":1776947505327,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":63,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,11,5]],"date-time":"2020-11-05T00:00:00Z","timestamp":1604534400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Department of Defense (DoD) Agency-Intelligence Advanced Research Projects Activity (IARPA)","award":["W911NF-17-9-0001"],"award-info":[{"award-number":["W911NF-17-9-0001"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,11,5]]},"DOI":"10.1145\/3414622.3431911","type":"proceedings-article","created":{"date-parts":[[2020,12,14]],"date-time":"2020-12-14T21:50:00Z","timestamp":1607982600000},"page":"1-7","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":35,"title":["Global interconnects in VLSI complexity single flux quantum systems"],"prefix":"10.1145","author":[{"given":"Tahereh","family":"Jabbari","sequence":"first","affiliation":[{"name":"University of Rochester"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eby G.","family":"Friedman","sequence":"additional","affiliation":[{"name":"University of Rochester"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,12,14]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/77.80745"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2014.2382665"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/77.763251"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2018.2797253"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/77.783712"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1142\/S0129156401000861"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2019.2903023"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2016.2519388"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2019.2898685"},{"key":"e_1_3_2_1_10_1","unstructured":"\"Predictive Technology Model (PTM).\" [Online]. Available: http:\/\/ptm.asu.edu\/  \"Predictive Technology Model (PTM).\" [Online]. Available: http:\/\/ptm.asu.edu\/"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2020.3000982"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2010.2098432"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2019.2891166"},{"issue":"5","key":"e_1_3_2_1_14_1","first-page":"1341","article-title":"The Josephson Transmission Line as an Impedance Matching Circuit","volume":"3","author":"Dimov B.","year":"2003","journal-title":"WSEAS Transactions on Circuits and Systems"},{"key":"e_1_3_2_1_15_1","first-page":"1465","volume-title":"Automation Test in Europe Conference","volume":"29","author":"Shahsavani S. N.","year":"2018"},{"key":"e_1_3_2_1_16_1","first-page":"1","article-title":"A Robust and Tree-Free Hybrid Clocking Technique for RSFQ circuits---CSR Application","author":"Tadros R. N.","year":"2017","journal-title":"Proceedings of the International Superconductive Electronics Conference"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2018.2793203"},{"key":"e_1_3_2_1_18_1","first-page":"384","article-title":"Design of Multiple Fanout Clock Distribution Network for Rapid Single Flux Quantum Technology","author":"Katam N.","year":"2017","journal-title":"Proceedings of the IEEE Asia and South Pacific Design Automation Conference"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2019.2943930"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2005.847487"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2005.849860"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2016.2598769"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2003.813929"},{"key":"e_1_3_2_1_24_1","first-page":"1","article-title":"Global Signaling for Large Scale RSFQ Circuits","author":"Jabbari T.","year":"2019","journal-title":"Proceedings of the Government Microcircuit Applications and Critical Technology Conference"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRev.108.1175"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1016\/0031-9163(62)91369-0"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.2810145"},{"key":"e_1_3_2_1_28_1","unstructured":"\"Niobium Process - Hypres Inc.\" [Online]. Available: https:\/\/www.hypres.com\/foundry\/niobium-process\/  \"Niobium Process - Hypres Inc.\" [Online]. Available: https:\/\/www.hypres.com\/foundry\/niobium-process\/"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0921-4534(02)00686-X"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.1987.1064951"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.5555\/299781"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevLett.3.552"},{"key":"e_1_3_2_1_33_1","unstructured":"\"Stony Brook RSFQ Cell Library.\" [Online]. Available: http:\/\/www.physics.sunysb.edu\/Physics\/RSFQ\/Lib\/PB\/msl.html  \"Stony Brook RSFQ Cell Library.\" [Online]. Available: http:\/\/www.physics.sunysb.edu\/Physics\/RSFQ\/Lib\/PB\/msl.html"},{"key":"e_1_3_2_1_34_1","article-title":"Splitter Trees in SFQ Circuits","author":"Jabbari T.","journal-title":"IEEE Transactions on Applied Superconductivity (in submission)."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/77.621825"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/77.892144"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2007.898606"},{"issue":"3","key":"e_1_3_2_1_38_1","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/TASC.2014.2369213","article-title":"Inductance of Circuit Structures for MIT LL Super-conductor Electronics Fabrication Process with 8 Niobium Layers","volume":"25","author":"Tolpygo S. K.","year":"2015","journal-title":"IEEE Transactions on Applied Superconductivity"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/77.892144"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2020.2964542"},{"key":"e_1_3_2_1_41_1","first-page":"2","article-title":"Development of Passive Interconnection Technology for SFQ Circuits","volume":"88","author":"Hashimoto Y.","year":"2005","journal-title":"IEICE Transactions on Electronics"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2009.2019284"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/81.886981"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/82.938357"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/77.622058"},{"key":"e_1_3_2_1_46_1","first-page":"1","article-title":"Progress Toward VLSI-Capable EDA Tools for Superconductive Digital Electronics","author":"Whiteley S. R.","year":"2019","journal-title":"Proceedings of the IEEE International Super-conductive Electronics Conference"},{"key":"e_1_3_2_1_47_1","volume-title":"Global Routing in Layout Design and Verification","author":"Kuh E. S.","year":"1986"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2007.898718"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2017.2675889"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2019.2909985"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/77.791915"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/77.403302"},{"key":"e_1_3_2_1_53_1","first-page":"302","article-title":"Two-Phase Clocking for Medium to Large RSFQ Circuits","author":"Gaj K.","year":"1997","journal-title":"Proceedings of the International Superconductive Electronics Conference"},{"key":"e_1_3_2_1_54_1","first-page":"39","article-title":"Choice of the Optimum Timing Scheme for RSFQ Digital Circuits","author":"Gaj K.","year":"1997","journal-title":"Proceedings of the International Workshop on High-Temperature Superconducting Electron Devices"},{"key":"e_1_3_2_1_55_1","volume-title":"October","author":"Jabbari T.","year":"2020"},{"key":"e_1_3_2_1_56_1","first-page":"1475","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems","author":"Friedman E. G.","year":"1993"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.1993.343019"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929649"},{"key":"e_1_3_2_1_59_1","first-page":"4.422","volume-title":"A Clock Tree Topology Extraction Algorithm for Improving the Tolerance of Clock Distribution Networks to Delay Uncertainty,\" Proceedings of the IEEE International Symposium on Circuits and Systems","author":"Velenis D.","year":"2001"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.893576"},{"key":"e_1_3_2_1_61_1","first-page":"13","article-title":"High-Speed Rapid-Single-Flux-Quantum Multiplexer and Demultiplexer Design and Testing","author":"Zheng L.","year":"2007","journal-title":"University of California at Berkeley"},{"key":"e_1_3_2_1_62_1","first-page":"82","article-title":"Design and Implementation of a RSFQ Superconductive Digital Electronics Cell Library","author":"Bakolo R. S.","year":"2011","journal-title":"University of Stellenbosch"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2019.2899792"}],"event":{"name":"SLIP '20: System-Level Interconnect - Problems and Pathfinding Workshop","location":"San Diego California","acronym":"SLIP '20","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CS"]},"container-title":["Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3414622.3431911","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3414622.3431911","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:03:13Z","timestamp":1750197793000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3414622.3431911"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,5]]},"references-count":63,"alternative-id":["10.1145\/3414622.3431911","10.1145\/3414622"],"URL":"https:\/\/doi.org\/10.1145\/3414622.3431911","relation":{},"subject":[],"published":{"date-parts":[[2020,11,5]]},"assertion":[{"value":"2020-12-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}