{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:24:37Z","timestamp":1750220677208,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":11,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,11,5]],"date-time":"2020-11-05T00:00:00Z","timestamp":1604534400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,11,5]]},"DOI":"10.1145\/3414622.3431912","type":"proceedings-article","created":{"date-parts":[[2020,12,14]],"date-time":"2020-12-14T21:50:00Z","timestamp":1607982600000},"page":"1-7","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Outlook of device and assembly technologies enabling high-performance mobile computing"],"prefix":"10.1145","author":[{"given":"Mustafa","family":"Badaroglu","sequence":"first","affiliation":[{"name":"Qualcomm"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,12,14]]},"reference":[{"volume-title":"IRDS 2020 edition. Online: https:\/\/irds.ieee.org\/editions\/2020","author":"IEEE","key":"e_1_3_2_1_1_1","unstructured":"IEEE IRDS 2020 edition. Online: https:\/\/irds.ieee.org\/editions\/2020 IEEE IRDS 2020 edition. Online: https:\/\/irds.ieee.org\/editions\/2020"},{"key":"e_1_3_2_1_2_1","volume-title":"September","author":"Badaroglu M.","year":"2017","unstructured":"M. Badaroglu , \" PPAC scaling enablement for 5nm mobile SoC technology,\" ESSDERC'2017 , September 2017 . M. Badaroglu et al., \"PPAC scaling enablement for 5nm mobile SoC technology,\" ESSDERC'2017, September 2017."},{"key":"e_1_3_2_1_3_1","volume-title":"December","author":"Auth C.","year":"2017","unstructured":"C. Auth , \" A 10nm high performance and low-power CMOS technology featuring 3rd-generation finFET transistors, self-aligned quad patterning, contact over active gate and Cobalt local interconnects,\" IEDM , December 2017 . C. Auth et al., \"A 10nm high performance and low-power CMOS technology featuring 3rd-generation finFET transistors, self-aligned quad patterning, contact over active gate and Cobalt local interconnects,\" IEDM, December 2017."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","unstructured":"S.K. Moore \"A better way to measure progress in semiconductors \" \"The node is nonsense \" IEEE Spectrum August 2020.  S.K. Moore \"A better way to measure progress in semiconductors \" \"The node is nonsense \" IEEE Spectrum August 2020.","DOI":"10.1109\/MSPEC.2020.9150552"},{"key":"e_1_3_2_1_5_1","unstructured":"M. Badaroglu \"3D IC opportunities for high-performance computing\" Semi 3D & Systems summit January 2020.  M. Badaroglu \"3D IC opportunities for high-performance computing\" Semi 3D & Systems summit January 2020."},{"key":"e_1_3_2_1_6_1","volume-title":"December","author":"Yeap G.","year":"2019","unstructured":"G. Yeap , \" 5nm CMOS production technology platform featuring full-fledged EUV, and high mobility channel FinFETs with densest 0.021 um2 SRAM cells for mobile SoC and high-performance computing applications,\" IEDM , December 2019 . G. Yeap et al., \"5nm CMOS production technology platform featuring full-fledged EUV, and high mobility channel FinFETs with densest 0.021 um2 SRAM cells for mobile SoC and high-performance computing applications,\" IEDM, December 2019."},{"issue":"6","key":"e_1_3_2_1_7_1","volume":"63","author":"Ciofi I.","year":"2016","unstructured":"I. Ciofi RC and circuit delay,\" IEEE J. Electron Devices , Vol. 63 , No. 6 , June 2016 . I. Ciofi et al., \"Impact of wire geometry on interconnect RC and circuit delay,\" IEEE J. Electron Devices, Vol. 63, No. 6, June 2016.","journal-title":"IEEE J. Electron Devices"},{"key":"e_1_3_2_1_8_1","volume-title":"VLSI Tech","author":"Song S.C.","year":"2016","unstructured":"S.C. Song technology optimization platform using integrated analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes,\" Symp . VLSI Tech , June 2016 . S.C. Song et al., \"Unified technology optimization platform using integrated analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes,\" Symp. VLSI Tech, June 2016."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"M. Badaroglu \"Interconnect-aware technology and design co-optimization for the 5-nm technology and beyond \" Journal of Low Power Electronics (JOLPE) Vol. 14 No. 2 June 2018.  M. Badaroglu \"Interconnect-aware technology and design co-optimization for the 5-nm technology and beyond \" Journal of Low Power Electronics (JOLPE) Vol. 14 No. 2 June 2018.","DOI":"10.1166\/jolpe.2018.1564"},{"key":"e_1_3_2_1_10_1","volume-title":"December","author":"Elsherbini A.A.","year":"2019","unstructured":"A.A. Elsherbini , \" Heterogeneous integration using omni-directional interconnect packaging,\" IEDM , December 2019 . A.A. Elsherbini et al., \"Heterogeneous integration using omni-directional interconnect packaging,\" IEDM, December 2019."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993626"}],"event":{"name":"SLIP '20: System-Level Interconnect - Problems and Pathfinding Workshop","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CS"],"location":"San Diego California","acronym":"SLIP '20"},"container-title":["Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3414622.3431912","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3414622.3431912","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:03:13Z","timestamp":1750197793000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3414622.3431912"}},"subtitle":["IRDS view (invited)"],"short-title":[],"issued":{"date-parts":[[2020,11,5]]},"references-count":11,"alternative-id":["10.1145\/3414622.3431912","10.1145\/3414622"],"URL":"https:\/\/doi.org\/10.1145\/3414622.3431912","relation":{},"subject":[],"published":{"date-parts":[[2020,11,5]]},"assertion":[{"value":"2020-12-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}