{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:23:02Z","timestamp":1750220582762,"version":"3.41.0"},"reference-count":51,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2020,9,27]],"date-time":"2020-09-27T00:00:00Z","timestamp":1601164800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Parallel Comput."],"published-print":{"date-parts":[[2020,12,31]]},"abstract":"<jats:p>Field Programmable Gate Arrays (FPGAs) are becoming an appealing technology in datacenters and High Performance Computing. High-Level Synthesis (HLS) of multi-threaded parallel programs is increasingly used to extract parallelism. Despite great leaps forward in HLS and related debugging methodologies, there is a lack of contributions in automated bug identification for HLS of multi-threaded programs. This work defines a methodology to automatically detect and isolate bugs in parallel circuits generated with HLS. The technique relies on hardware\/software Discrepancy Analysis and exploits a pattern-matching algorithm based on Finite State Automata to compare multiple hardware and software threads. Overhead, advantages, and limitations are evaluated on designs generated with an open-source HLS compiler supporting OpenMP.<\/jats:p>","DOI":"10.1145\/3418086","type":"journal-article","created":{"date-parts":[[2020,9,27]],"date-time":"2020-09-27T22:10:11Z","timestamp":1601244611000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular Applications"],"prefix":"10.1145","volume":"7","author":[{"given":"Pietro","family":"Fezzardi","sequence":"first","affiliation":[{"name":"Dipartimento di Informazione, Elettronica e Bioingegneria \u2013 Politecnico di Milano, Milano, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fabrizio","family":"Ferrandi","sequence":"additional","affiliation":[{"name":"Dipartimento di Informazione, Elettronica e Bioingegneria \u2013 Politecnico di Milano, Milano, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,9,27]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"IEEE. 2016. Standard for information technology\u2014Portable operating system interface (POSIX) base specifications Issue 7. IEEE Std 1003.1 2016 Edition (incorporates IEEE Std 1003.1-2008 IEEE Std 1003.1-2008\/Cor 1-2013 and IEEE Std 1003.1-2008\/Cor 2-2016) (Sept. 2016) 1--3957.  IEEE. 2016. Standard for information technology\u2014Portable operating system interface (POSIX) base specifications Issue 7. IEEE Std 1003.1 2016 Edition (incorporates IEEE Std 1003.1-2008 IEEE Std 1003.1-2008\/Cor 1-2013 and IEEE Std 1003.1-2008\/Cor 2-2016) (Sept. 2016) 1--3957."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.912106"},{"key":"e_1_2_1_3_1","unstructured":"The OpenMP Architecture Review Board. 2015. OpenMP Application Programming Interface\u2014Version 4.5. Retrieved from http:\/\/www.openmp.org\/wp-content\/uploads\/openmp-4.5.pdf.  The OpenMP Architecture Review Board. 2015. OpenMP Application Programming Interface\u2014Version 4.5. Retrieved from http:\/\/www.openmp.org\/wp-content\/uploads\/openmp-4.5.pdf."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/295545.295551"},{"volume-title":"Proceedings of the International Symposium on Systems, Architectures, Modeling, and Simulation. 17--24","author":"Cabrera D.","key":"e_1_2_1_5_1"},{"volume-title":"Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL\u201914)","author":"Calagar N.","key":"e_1_2_1_6_1"},{"volume-title":"Proceedings of the 53rd Annual Design Automation Conference (DAC\u201916)","author":"Campbell K.","key":"e_1_2_1_7_1"},{"volume-title":"Proceedings of the 52nd Annual Design Automation Conference (DAC\u201915)","author":"Campbell K.","key":"e_1_2_1_8_1"},{"volume-title":"Proceedings of the International Conference on Field-programmable Technology (FPT\u201913)","author":"Castellana V. G.","key":"e_1_2_1_9_1"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3288754"},{"volume-title":"Proceedings of the International Conference on Field-programmable Technology (FPT\u201913)","author":"Choi J.","key":"e_1_2_1_11_1"},{"volume-title":"Proceedings of the IEEE International Symposium on Parallel Distributed Processing, Workshops and PhD Forum (IPDPSW\u201910)","author":"Curreri J.","key":"e_1_2_1_12_1"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/115372.115320"},{"volume-title":"Proceedings of the 33rd IEEE International Conference on Computer Design (ICCD\u201915)","author":"Fezzardi P.","key":"e_1_2_1_14_1"},{"volume-title":"Proceedings of the 26th International Conference on Field Programmable Logic and Applications (FPL\u201916)","author":"Fezzardi P.","key":"e_1_2_1_15_1"},{"key":"e_1_2_1_16_1","doi-asserted-by":"crossref","unstructured":"P. Fezzardi M. Lattuada and F. Ferrandi. 2017. Using efficient path profiling to optimize memory consumption of on-chip debugging for high-level synthesis. ACM Trans. Embed. Comput. Syst. (Special Issue on ESWEEK\u201917) 1--19. Retrieved from https:\/\/re.public.polimi.it\/retrieve\/handle\/11311\/1030731\/222692\/EPPDiscrepancyAnalysis.pdf.  P. Fezzardi M. Lattuada and F. Ferrandi. 2017. Using efficient path profiling to optimize memory consumption of on-chip debugging for high-level synthesis. ACM Trans. Embed. Comput. Syst. (Special Issue on ESWEEK\u201917) 1--19. Retrieved from https:\/\/re.public.polimi.it\/retrieve\/handle\/11311\/1030731\/222692\/EPPDiscrepancyAnalysis.pdf.","DOI":"10.1145\/3126564"},{"key":"e_1_2_1_17_1","unstructured":"Intel FPGA. 2017. Intel FPGA SDK for OpenCL\u2014Programming Guide. Retrieved from https:\/\/www.altera.com\/content\/dam\/altera-www\/global\/en_US\/pdfs\/literature\/hb\/opencl-sdk\/aocl_programming_guide.pdf.  Intel FPGA. 2017. Intel FPGA SDK for OpenCL\u2014Programming Guide. Retrieved from https:\/\/www.altera.com\/content\/dam\/altera-www\/global\/en_US\/pdfs\/literature\/hb\/opencl-sdk\/aocl_programming_guide.pdf."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.25"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2015.7393128"},{"key":"e_1_2_1_20_1","unstructured":"Mentor Graphics. 2017. Catapult C High Level Synthesis HLS Verification. Retrieved from https:\/\/www.mentor.com\/hls-lp\/catapult-high-level-synthesis\/hls-verification.  Mentor Graphics. 2017. Catapult C High Level Synthesis HLS Verification. Retrieved from https:\/\/www.mentor.com\/hls-lp\/catapult-high-level-synthesis\/hls-verification."},{"key":"e_1_2_1_21_1","unstructured":"Khronos OpenCL Working Group. 2017. The OpenCL Specification\u2014Version 2.2. Retrieved from https:\/\/www.khronos.org\/registry\/OpenCL\/specs\/opencl-2.2.pdf.  Khronos OpenCL Working Group. 2017. The OpenCL Specification\u2014Version 2.2. Retrieved from https:\/\/www.khronos.org\/registry\/OpenCL\/specs\/opencl-2.2.pdf."},{"volume-title":"Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES\u201913)","author":"Halstead R. J.","key":"e_1_2_1_22_1"},{"key":"e_1_2_1_23_1","first-page":"3","article-title":"A unified design flow to automatically generate on-chip monitors during high-level synthesis of hardware accelerators","volume":"36","author":"Hammouda M. B.","year":"2017","journal-title":"IEEE Trans. Comput.-aided Des. Integ. Circ. Syst."},{"volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS\u201908)","author":"Hara Y.","key":"e_1_2_1_24_1"},{"volume-title":"Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL\u201915)","author":"Hosseinabady M.","key":"e_1_2_1_25_1"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2618862"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2567662"},{"volume-title":"Proceedings of the ACM\/SIGDA International Symposium on Field-programmable Gate Arrays (FPGA\u201918)","author":"Jamal Al-Shahna","key":"e_1_2_1_28_1"},{"volume-title":"Proceedings of the IEEE 23rd Annual International Symposium on Field-programmable Custom Computing Machines. 195--198","author":"Korinth J.","key":"e_1_2_1_29_1"},{"volume-title":"Proceedings of the International Symposium on Code Generation and Optimization (CGO\u201904)","author":"Lattner C.","key":"e_1_2_1_30_1"},{"volume-title":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs. 1--6.","author":"Ma S.","key":"e_1_2_1_31_1"},{"volume-title":"Proceedings of the International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201916)","author":"Minutoli M.","key":"e_1_2_1_32_1"},{"volume-title":"Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL\u201914)","author":"Monson J. S.","key":"e_1_2_1_33_1"},{"volume-title":"Proceedings of the ACM\/SIGDA International Symposium on Field-programmable Gate Arrays (FPGA\u201915)","author":"Monson J. S.","key":"e_1_2_1_34_1"},{"key":"e_1_2_1_35_1","first-page":"1","article-title":"A survey and evaluation of FPGA high-level synthesis tools","volume":"99","author":"Nane R.","year":"2016","journal-title":"IEEE Trans. Comput.-aided Des. Integ. Circ. Syst. PP"},{"key":"e_1_2_1_36_1","unstructured":"NEC. 2016. CyberWorkbench: NEC\u2019s High Level Synthesis Solution. Retrieved from http:\/\/www.nec.com\/en\/global\/prod\/cwb\/pdf\/CWB_Detailed_technical.pdf.  NEC. 2016. CyberWorkbench: NEC\u2019s High Level Synthesis Solution. Retrieved from http:\/\/www.nec.com\/en\/global\/prod\/cwb\/pdf\/CWB_Detailed_technical.pdf."},{"volume-title":"Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI\u201916)","author":"Nguyen T.","key":"e_1_2_1_37_1"},{"key":"e_1_2_1_38_1","unstructured":"NVIDIA. 2017. CUDA Parallel Programming and Computing Platform. Retrieved from http:\/\/www.nvidia.com\/object\/cuda_home_new.html.  NVIDIA. 2017. CUDA Parallel Programming and Computing Platform. Retrieved from http:\/\/www.nvidia.com\/object\/cuda_home_new.html."},{"volume-title":"Proceedings of the IEEE 19th Annual International Symposium on Field-programmable Custom Computing Machines. 186--193","author":"Owaida M.","key":"e_1_2_1_39_1"},{"volume-title":"Proceedings of the ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA\u201914)","author":"Putnam A.","key":"e_1_2_1_40_1"},{"volume-title":"Proceedings of the FDL Forum on Specification, Verification and Design Languages. 1--8.","author":"Ribon A.","key":"e_1_2_1_41_1"},{"key":"e_1_2_1_42_1","first-page":"1","article-title":"Source code error detection in high-level synthesis functional verification","volume":"24","author":"Schafer B. Carrion","year":"2016","journal-title":"IEEE Trans. Very Large Scale Integ. (VLSI) Syst."},{"issue":"3","key":"e_1_2_1_43_1","first-page":"3","article-title":"Using the GNU Compiler Collection","volume":"4","author":"Stallman R. M.","year":"2009","journal-title":"A GNU Manual for GCC Version"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2016.2544850"},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-aided Design (ICCAD\u201914)","author":"Tan M.","key":"e_1_2_1_45_1"},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1997.582405"},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062230"},{"volume-title":"Proceedings of the International Conference on Field-programmable Technology. 269--276","author":"Wang Y.","key":"e_1_2_1_48_1"},{"key":"e_1_2_1_49_1","unstructured":"Xilinx. 2017. The SDAccel Development Environment for OpenCL. Retrieved from https:\/\/www.xilinx.com\/products\/design-tools\/software-zone\/sdaccel.html.  Xilinx. 2017. The SDAccel Development Environment for OpenCL. Retrieved from https:\/\/www.xilinx.com\/products\/design-tools\/software-zone\/sdaccel.html."},{"volume-title":"Proceedings of the IEEE 24th Annual International Symposium on Field-programmable Custom Computing Machines (FCCM\u201916)","author":"Yang L.","key":"e_1_2_1_50_1"},{"volume-title":"Proceedings of the International Conference on Field Programmable Technology (FPT\u201915)","author":"Yang L.","key":"e_1_2_1_51_1"}],"container-title":["ACM Transactions on Parallel Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3418086","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3418086","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:31:35Z","timestamp":1750195895000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3418086"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,27]]},"references-count":51,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2020,12,31]]}},"alternative-id":["10.1145\/3418086"],"URL":"https:\/\/doi.org\/10.1145\/3418086","relation":{},"ISSN":["2329-4949","2329-4957"],"issn-type":[{"type":"print","value":"2329-4949"},{"type":"electronic","value":"2329-4957"}],"subject":[],"published":{"date-parts":[[2020,9,27]]},"assertion":[{"value":"2018-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-06-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-09-27","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}