{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,31]],"date-time":"2026-01-31T06:07:37Z","timestamp":1769839657896,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":45,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,9,28]],"date-time":"2020-09-28T00:00:00Z","timestamp":1601251200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Triad National Security, LLC","award":["81326"],"award-info":[{"award-number":["81326"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,9,28]]},"DOI":"10.1145\/3422575.3422806","type":"proceedings-article","created":{"date-parts":[[2021,3,22]],"date-time":"2021-03-22T01:43:40Z","timestamp":1616377420000},"page":"341-351","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["PPT-SASMM: Scalable Analytical Shared Memory Model"],"prefix":"10.1145","author":[{"given":"Atanu","family":"Barai","sequence":"first","affiliation":[{"name":"New Mexico State University, United States"}]},{"given":"Gopinath","family":"Chennupati","sequence":"additional","affiliation":[{"name":"Los Alamos National Laboratory, United States"}]},{"given":"Nandakishore","family":"Santhi","sequence":"additional","affiliation":[{"name":"Los Alamos National Laboratory, United States"}]},{"given":"Abdel-Hameed","family":"Badawy","sequence":"additional","affiliation":[{"name":"New Mexico State University, United States"}]},{"given":"Yehia","family":"Arafa","sequence":"additional","affiliation":[{"name":"New Mexico State University, United States"}]},{"given":"Stephan","family":"Eidenbenz","sequence":"additional","affiliation":[{"name":"Los Alamos National Laboratory, United States"}]}],"member":"320","published-online":{"date-parts":[[2021,3,21]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/3392717.3392761"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPCCC47392.2019.8958760"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/1153925.1154584"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2006.1620793"},{"key":"e_1_3_2_1_5_1","volume-title":"In Proceedings of the IASTED Conference on Parallel and Distributed Computing and Systems. IEEE","author":"Beyls Kristof","year":"2001","unstructured":"Kristof Beyls and Erik\u00a0 H. D\u2019Hollander . 2001 . Reuse Distance as a Metric for Cache Behavior . In In Proceedings of the IASTED Conference on Parallel and Distributed Computing and Systems. IEEE , Piscataway, NJ, USA, 617\u2013662. Kristof Beyls and Erik\u00a0H. D\u2019Hollander. 2001. Reuse Distance as a Metric for Cache Behavior. In In Proceedings of the IASTED Conference on Parallel and Distributed Computing and Systems. IEEE, Piscataway, NJ, USA, 617\u2013662."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/782814.782836"},{"key":"e_1_3_2_1_9_1","volume-title":"Algorithms and Architectures for Parallel Processing","author":"Ceballos Germ\u00e1n","unstructured":"Germ\u00e1n Ceballos , Erik Hagersten , and David Black-Schaffer . 2016. Formalizing Data Locality in Task Parallel Applications . In Algorithms and Architectures for Parallel Processing . Springer International Publishing , Cham , 43\u201361. Germ\u00e1n Ceballos, Erik Hagersten, and David Black-Schaffer. 2016. Formalizing Data Locality in Task Parallel Applications. In Algorithms and Architectures for Parallel Processing. Springer International Publishing, Cham, 43\u201361."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_3_2_1_11_1","volume-title":"A Scalable Analytical Memory Model for CPU Performance Prediction","author":"Chennupati Gopinath","unstructured":"Gopinath Chennupati , Nandakishore Santhi , Robert Bird , Sunil Thulasidasan , Abdel-Hameed\u00a0 A. Badawy , Satyajayant Misra , and Stephan Eidenbenz . 2018. A Scalable Analytical Memory Model for CPU Performance Prediction . In High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation, Stephen Jarvis, Steven Wright, and Simon Hammond (Eds.). Springer International Publishing , Cham , 114\u2013135. Gopinath Chennupati, Nandakishore Santhi, Robert Bird, Sunil Thulasidasan, Abdel-Hameed\u00a0A. Badawy, Satyajayant Misra, and Stephan Eidenbenz. 2018. A Scalable Analytical Memory Model for CPU Performance Prediction. In High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation, Stephen Jarvis, Steven Wright, and Simon Hammond (Eds.). Springer International Publishing, Cham, 114\u2013135."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316480.3325518"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/3242181.3242251"},{"key":"e_1_3_2_1_14_1","unstructured":"Gopinath Chennupati Nanadakishore Santhi Stephen Eidenbenz Robert\u00a0Joseph Zerr Massimiliano Rosa Richard\u00a0James Zamora Eun\u00a0Jung Park Balasubramanya\u00a0T. Nadiga Jason Liu Kishwar Ahmed and Mohammad\u00a0Abu Obaida. 2017c. Performance Prediction Toolkit (PPT). Los Alamos National Laboratory (LANL). https:\/\/github.com\/lanl\/PPT.  Gopinath Chennupati Nanadakishore Santhi Stephen Eidenbenz Robert\u00a0Joseph Zerr Massimiliano Rosa Richard\u00a0James Zamora Eun\u00a0Jung Park Balasubramanya\u00a0T. Nadiga Jason Liu Kishwar Ahmed and Mohammad\u00a0Abu Obaida. 2017c. Performance Prediction Toolkit (PPT). Los Alamos National Laboratory (LANL). https:\/\/github.com\/lanl\/PPT."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/99.660313"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2818374"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2005.42"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2017.2701370"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-014-1460-7"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/781131.781159"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.43"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2003.1240600"},{"key":"e_1_3_2_1_25_1","volume-title":"Auto-tuning a high-level language targeted to GPU codes. In 2012 Innovative Parallel Computing (InPar)","author":"Grauer-Gray Scott","unstructured":"Scott Grauer-Gray , Lifan Xu , Robert Searles , Sudhee Ayalasomayajula , and John Cavazos . 2012. Auto-tuning a high-level language targeted to GPU codes. In 2012 Innovative Parallel Computing (InPar) . IEEE , Piscataway, NJ, USA , 1\u201310. Scott Grauer-Gray, Lifan Xu, Robert Searles, Sudhee Ayalasomayajula, and John Cavazos. 2012. Auto-tuning a high-level language targeted to GPU codes. In 2012 Innovative Parallel Computing (InPar). IEEE, Piscataway, NJ, USA, 1\u201310."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.5555\/645988.674164"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-11970-5_15"},{"key":"e_1_3_2_1_28_1","volume-title":"Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No. PR00550)","author":"Kaxiras Stefanos","year":"2000","unstructured":"Stefanos Kaxiras and Cliff Young . 2000 . Coherence communication prediction in shared-memory multiprocessors . In Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No. PR00550) . IEEE, IEEE, Piscataway, NJ, USA, 156\u2013167. Stefanos Kaxiras and Cliff Young. 2000. Coherence communication prediction in shared-memory multiprocessors. In Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No. PR00550). IEEE, IEEE, Piscataway, NJ, USA, 156\u2013167."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601909"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.5555\/977395.977673"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-13217-9_2"},{"key":"e_1_3_2_1_32_1","volume-title":"Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE","author":"Maeda Rafael","year":"2017","unstructured":"Rafael K.\u00a0V. Maeda , Qiong Cai , Jiang Xu , Zhe Wang , and Zhongyuan Tian . 2017 . Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE , Piscataway, NJ, USA, 145\u2013156. Rafael K.\u00a0V. Maeda, Qiong Cai, Jiang Xu, Zhe Wang, and Zhongyuan Tian. 2017. Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, Piscataway, NJ, USA, 145\u2013156."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1147\/sj.92.0078"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1273442.1250746"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2012.117"},{"key":"e_1_3_2_1_36_1","volume-title":"Polybench: The polyhedral benchmark suite. URL: http:\/\/www.cs.ucla.edu\/pouchet\/software\/polybench","author":"Pouchet Louis-No\u00ebl","year":"2012","unstructured":"Louis-No\u00ebl Pouchet . 2012 . Polybench: The polyhedral benchmark suite. URL: http:\/\/www.cs.ucla.edu\/pouchet\/software\/polybench (2012). Louis-No\u00ebl Pouchet. 2012. Polybench: The polyhedral benchmark suite. URL: http:\/\/www.cs.ucla.edu\/pouchet\/software\/polybench (2012)."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1275571.1275600"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2019.2896633"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854286"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2010.5470780"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/2494232.2465756"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.5555\/1964238.1964240"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/1190216.1190227"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2009.31"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024723.2000109"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2547387"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/2427631.2427632"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.50"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/1552309.1552310"}],"event":{"name":"MEMSYS 2020: The International Symposium on Memory Systems","location":"Washington DC USA","acronym":"MEMSYS 2020"},"container-title":["The International Symposium on Memory Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3422575.3422806","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3422575.3422806","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:01:55Z","timestamp":1750197715000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3422575.3422806"}},"subtitle":["Predicting the Performance of Multicore Caches from a Single-Threaded Execution Trace"],"short-title":[],"issued":{"date-parts":[[2020,9,28]]},"references-count":45,"alternative-id":["10.1145\/3422575.3422806","10.1145\/3422575"],"URL":"https:\/\/doi.org\/10.1145\/3422575.3422806","relation":{},"subject":[],"published":{"date-parts":[[2020,9,28]]},"assertion":[{"value":"2021-03-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}