{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,29]],"date-time":"2026-09-29T09:43:51Z","timestamp":1790675031077,"version":"4.1.0"},"reference-count":38,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2021,2,17]],"date-time":"2021-02-17T00:00:00Z","timestamp":1613520000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Science Foundation","award":["CNS 1955353, CNS 1564014"],"award-info":[{"award-number":["CNS 1955353, CNS 1564014"]}]},{"name":"ARO","award":["W911NF-17-1-0485"],"award-info":[{"award-number":["W911NF-17-1-0485"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2021,3,31]]},"abstract":"<jats:p>\n            Heterogeneous manycore architectures are the key to efficiently execute compute- and data-intensive applications. Through-silicon-via (TSV)-based 3D manycore system is a promising solution in this direction as it enables the integration of disparate computing cores on a single system. Recent industry trends show the viability of 3D integration in real products (e.g., Intel Lakefield SoC Architecture, the AMD Radeon R9 Fury X graphics card, and Xilinx Virtex-7 2000T\/H580T, etc.). However, the achievable performance of conventional TSV-based 3D systems is ultimately bottlenecked by the horizontal wires (wires in each planar die). Moreover, current TSV 3D architectures suffer from thermal limitations. Hence, TSV-based architectures do not realize the full potential of 3D integration. Monolithic 3D (M3D) integration, a breakthrough technology to achieve \u201cMore Moore and More Than Moore,\u201d opens up the possibility of designing cores and associated network routers using multiple layers by utilizing monolithic inter-tier vias (MIVs) and hence, reducing the effective wire length. Compared to TSV-based 3D integrated circuits (ICs), M3D offers the \u201ctrue\u201d benefits of vertical dimension for system integration: the size of an MIV used in M3D is over 100 \u00d7 smaller than a TSV. This dramatic reduction in via size and the resulting increase in density opens up numerous opportunities for design optimizations in 3D manycore systems: designers can use up to millions of MIVs for ultra-fine-grained 3D optimization, where individual cores and routers can be spread across multiple tiers for extreme power and performance optimization. In this work, we demonstrate how M3D-enabled vertical core and uncore elements offer significant performance and thermal improvements in manycore heterogeneous architectures compared to its TSV-based counterpart. To overcome the difficult optimization challenges due to the large design space and complex interactions among the heterogeneous components (CPU, GPU, Last Level Cache, etc.) in a M3D-based manycore chip, we leverage novel design-space exploration algorithms to trade off different objectives. The proposed M3D-enabled heterogeneous architecture, called\n            <jats:italic>HeM3D<\/jats:italic>\n            , outperforms its state-of-the-art TSV-equivalent counterpart by up to 18.3% in execution time while being up to 19\u00b0C cooler.\n          <\/jats:p>","DOI":"10.1145\/3424239","type":"journal-article","created":{"date-parts":[[2021,2,20]],"date-time":"2021-02-20T22:42:52Z","timestamp":1613860972000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["HeM3D"],"prefix":"10.1145","volume":"26","author":[{"given":"Aqeeb Iqbal","family":"Arka","sequence":"first","affiliation":[{"name":"Washington State University, Pullman, WA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Biresh Kumar","family":"Joardar","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ryan Gary","family":"Kim","sequence":"additional","affiliation":[{"name":"Colorado State University, Fort Collins, CO"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dae Hyun","family":"Kim","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Janardhan Rao","family":"Doppa","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Partha Pratim","family":"Pande","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2021,2,17]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.cam.2014.02.022"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/SAAHPC.2011.29"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"e_1_2_1_4_1","doi-asserted-by":"crossref","unstructured":"S. K. Samal D. Nayak M. Ichihashi S. Banna and S. K. Lim. 2016. Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology. In 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 1--2. DOI:https:\/\/doi.org\/10.1109\/S3S.2016.7804405  S. K. Samal D. Nayak M. Ichihashi S. Banna and S. K. Lim. 2016. Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology. In 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 1--2. 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