{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,16]],"date-time":"2026-04-16T01:43:51Z","timestamp":1776303831548,"version":"3.50.1"},"reference-count":68,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2020,12,30]],"date-time":"2020-12-30T00:00:00Z","timestamp":1609286400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2021,3,31]]},"abstract":"<jats:p>Accelerator design is expensive due to the effort required to understand an algorithm and optimize the design. Architects have embraced two technologies to reduce costs. High-level synthesis automatically generates hardware from code. Reconfigurable fabrics instantiate accelerators while avoiding fabrication costs for custom circuits. We further reduce design effort with statistical learning. We build an automated framework, called Prospector, that uses Bayesian techniques to optimize synthesis directives, reducing execution latency and resource usage in field-programmable gate arrays. We show in a certain amount of time that designs discovered by Prospector are closer to Pareto-efficient designs compared to prior approaches. Prospector permits new studies for heterogeneous accelerators.<\/jats:p>","DOI":"10.1145\/3427377","type":"journal-article","created":{"date-parts":[[2020,12,30]],"date-time":"2020-12-30T12:30:51Z","timestamp":1609331451000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Bayesian Optimization for Efficient Accelerator Synthesis"],"prefix":"10.1145","volume":"18","author":[{"given":"Atefeh","family":"Mehrabi","sequence":"first","affiliation":[{"name":"Duke University, Durham, NC"}]},{"given":"Aninda","family":"Manocha","sequence":"additional","affiliation":[{"name":"Princeton University"}]},{"given":"Benjamin C.","family":"Lee","sequence":"additional","affiliation":[{"name":"University of Pennsylvania"}]},{"given":"Daniel J.","family":"Sorin","sequence":"additional","affiliation":[{"name":"Duke University, Durham, NC"}]}],"member":"320","published-online":{"date-parts":[[2020,12,30]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2007.01.004"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.844118"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/3197978"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/2188385.2188395"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2003.810761"},{"key":"e_1_2_1_7_1","volume-title":"A tutorial on Bayesian optimization of expensive cost functions, with application to active user modeling and hierarchical reinforcement learning. arXiv preprint arXiv:1012.2599","author":"Brochu E.","year":"2010","unstructured":"E. Brochu , V. Cora , and N. De Freitas . 2010. A tutorial on Bayesian optimization of expensive cost functions, with application to active user modeling and hierarchical reinforcement learning. arXiv preprint arXiv:1012.2599 ( 2010 ). E. Brochu, V. Cora, and N. De Freitas. 2010. A tutorial on Bayesian optimization of expensive cost functions, with application to active user modeling and hierarchical reinforcement learning. arXiv preprint arXiv:1012.2599 (2010)."},{"key":"e_1_2_1_8_1","volume-title":"Proc. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS\u201914)","author":"Chen T.","unstructured":"T. Chen , Z. Du , N. Sun , J. Wang , C. Wu , Y. Chen , and O. Temam . 2014. DianNao: A small-footprint high-throughput accelerator for ubiquitous machine-learning . In Proc. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS\u201914) . T. Chen, Z. Du, N. Sun, J. Wang, C. Wu, Y. Chen, and O. Temam. 2014. DianNao: A small-footprint high-throughput accelerator for ubiquitous machine-learning. In Proc. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS\u201914)."},{"key":"e_1_2_1_9_1","volume-title":"Proc. of the 53rd Annual Design Automation Conference.","author":"Choi Y.","unstructured":"Y. Choi , J. Cong , Z. Fang , Y. Hao , G. Reinman , and P. Wei . 2016. A quantitative analysis on microarchitectures of modern CPU-FPGA platforms . In Proc. of the 53rd Annual Design Automation Conference. Y. Choi, J. Cong, Z. Fang, Y. Hao, G. Reinman, and P. Wei. 2016. A quantitative analysis on microarchitectures of modern CPU-FPGA platforms. In Proc. of the 53rd Annual Design Automation Conference."},{"key":"e_1_2_1_10_1","volume-title":"Proc. International Symposium on Microarchitecture (MICRO\u201910)","author":"Chung E.","unstructured":"E. Chung , P. Milder , J. Hoe , and K. Mai . 2010. Single-chip heterogeneous computing: Does the future include custom logic, FGPAs, and GPGPUs? In Proc. International Symposium on Microarchitecture (MICRO\u201910) . E. Chung, P. Milder, J. Hoe, and K. Mai. 2010. Single-chip heterogeneous computing: Does the future include custom logic, FGPAs, and GPGPUs? In Proc. International Symposium on Microarchitecture (MICRO\u201910)."},{"key":"e_1_2_1_11_1","volume-title":"Proc. International SOC Conference (SOCC\u201906)","author":"Cong J.","unstructured":"J. Cong , Y. Fan , G. Han , W. Jiang , and Z. Zhang . 2006. Platform-based behavior-level and system-level synthesis . In Proc. International SOC Conference (SOCC\u201906) . J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang. 2006. Platform-based behavior-level and system-level synthesis. In Proc. International SOC Conference (SOCC\u201906)."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/4235.996017"},{"key":"e_1_2_1_14_1","volume-title":"Proc. International Symposium on Microarchitecture (MICRO\u201908)","author":"Dubach C.","unstructured":"C. Dubach , T. Jones , and M. O\u2019Boyle . 2008. Microarchitectural design space exploration using an architecture-centric approach . In Proc. International Symposium on Microarchitecture (MICRO\u201908) . C. Dubach, T. Jones, and M. O\u2019Boyle. 2008. Microarchitectural design space exploration using an architecture-centric approach. In Proc. International Symposium on Microarchitecture (MICRO\u201908)."},{"key":"e_1_2_1_15_1","volume-title":"Proc. Design Automation 8 Test in Europe Conference","volume":"1","author":"Eyerman S.","unstructured":"S. Eyerman , L. Eeckhout , and K. De Bosschere . 2006. Efficient design space exploration of high performance embedded out-of-order processors . In Proc. Design Automation 8 Test in Europe Conference , Vol. 1 . IEEE, 1--6. S. Eyerman, L. Eeckhout, and K. De Bosschere. 2006. Efficient design space exploration of high performance embedded out-of-order processors. In Proc. Design Automation 8 Test in Europe Conference, Vol. 1. IEEE, 1--6."},{"key":"e_1_2_1_16_1","volume-title":"2018 IEEE 36th International Conference on Computer Design (ICCD\u201918)","author":"Ferretti L.","unstructured":"L. Ferretti , G. Ansaloni , and L. Pozzi . 2018. Lattice-traversing design space exploration for high level synthesis . In 2018 IEEE 36th International Conference on Computer Design (ICCD\u201918) . IEEE, 210--217. L. Ferretti, G. Ansaloni, and L. Pozzi. 2018. Lattice-traversing design space exploration for high level synthesis. In 2018 IEEE 36th International Conference on Computer Design (ICCD\u201918). IEEE, 210--217."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/2503308.2503311"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1027084.1027086"},{"key":"e_1_2_1_19_1","unstructured":"P. Greenhalgh. 2011. Big. little processing with arm cortex-a15 8 cortex-a7. ARM White Paper.  P. Greenhalgh. 2011. Big. little processing with arm cortex-a15 8 cortex-a7. ARM White Paper."},{"key":"e_1_2_1_20_1","volume-title":"Proc. International Conference on Field Programmable Logic and Applications (FPL\u201916)","author":"Gupta P.","year":"2016","unstructured":"P. Gupta . 2016 . Accelerating datacenter workloads . In Proc. International Conference on Field Programmable Logic and Applications (FPL\u201916) . P. Gupta. 2016. Accelerating datacenter workloads. In Proc. International Conference on Field Programmable Logic and Applications (FPL\u201916)."},{"key":"e_1_2_1_21_1","volume-title":"Proc. International Symposium on Computer Architecture (ISCA\u201910)","author":"Hameed R.","unstructured":"R. Hameed , W. Qadeer , M. Wachs , O. Azizi , A. Solomatnikov , B. Lee , S. Richardson , C. Kozyraki , and M. Horowitz . 2010. Understanding sources of inefficiency in general-purpose chips . In Proc. International Symposium on Computer Architecture (ISCA\u201910) . R. Hameed, W. Qadeer, M. Wachs, O. Azizi, A. Solomatnikov, B. Lee, S. Richardson, C. Kozyraki, and M. Horowitz. 2010. Understanding sources of inefficiency in general-purpose chips. In Proc. International Symposium on Computer Architecture (ISCA\u201910)."},{"key":"e_1_2_1_22_1","volume-title":"Proc. International Conference on Machine Learning.","author":"Hern\u00e1ndez-Lobato D.","unstructured":"D. Hern\u00e1ndez-Lobato , J. Hern\u00e1ndez-Lobato , A. Shah , and R. Adams . 2016. Predictive entropy search for multi-objective Bayesian optimization . In Proc. International Conference on Machine Learning. D. Hern\u00e1ndez-Lobato, J. Hern\u00e1ndez-Lobato, A. Shah, and R. Adams. 2016. Predictive entropy search for multi-objective Bayesian optimization. In Proc. International Conference on Machine Learning."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2996866"},{"key":"e_1_2_1_24_1","volume-title":"Proc. ACM Symposium on Cloud Computing.","author":"Huang M.","unstructured":"M. Huang , D. Wu , C. Yu , Z. Fang , M. Interlandi , T. Condie , and J. Cong . 2016. Programming and runtime support to blaze FPGA accelerator deployment at datacenter scale . In Proc. ACM Symposium on Cloud Computing. M. Huang, D. Wu, C. Yu, Z. Fang, M. Interlandi, T. Condie, and J. Cong. 2016. Programming and runtime support to blaze FPGA accelerator deployment at datacenter scale. In Proc. ACM Symposium on Cloud Computing."},{"key":"e_1_2_1_25_1","volume-title":"Proc. International Symposium on Microarchitecture (MICRO\u201906)","author":"Joseph P.","unstructured":"P. Joseph , K. Vaswani , and M. Thazhuthaveetil . 2006. A predictive performance model for superscalar processors . In Proc. International Symposium on Microarchitecture (MICRO\u201906) . P. Joseph, K. Vaswani, and M. Thazhuthaveetil. 2006. A predictive performance model for superscalar processors. In Proc. International Symposium on Microarchitecture (MICRO\u201906)."},{"key":"e_1_2_1_26_1","volume-title":"Proc. 24th Symposium on Computer Arithmetic (ARITH\u201917)","author":"Koenig J","unstructured":"J Koenig , D. Biancolin , J. Bachrach , and K. Asanovic . 2017. A hardware accelerator for computing an exact dot product . In Proc. 24th Symposium on Computer Arithmetic (ARITH\u201917) . J Koenig, D. Biancolin, J. Bachrach, and K. Asanovic. 2017. A hardware accelerator for computing an exact dot product. In Proc. 24th Symposium on Computer Arithmetic (ARITH\u201917)."},{"key":"e_1_2_1_27_1","volume-title":"Proc. International Symposium on Computer Architecture (ISCA\u201916)","author":"Koeplinger D.","unstructured":"D. Koeplinger , R. Prabhakar , Y. Zhang , C. Delimitrou , C. Kozyrakis , and K. Olukotun . 2016. Automatic generation of efficient accelerators for reconfigurable hardware . In Proc. International Symposium on Computer Architecture (ISCA\u201916) . D. Koeplinger, R. Prabhakar, Y. Zhang, C. Delimitrou, C. Kozyrakis, and K. Olukotun. 2016. Automatic generation of efficient accelerators for reconfigurable hardware. In Proc. International Symposium on Computer Architecture (ISCA\u201916)."},{"key":"e_1_2_1_28_1","volume-title":"Proc. International Symposium on Microarchitecture (MICRO\u201903)","author":"Kumar R.","unstructured":"R. Kumar , K. Farkas , N. Jouppi , P. Ranganathan , and D. Tullsen . 2003. Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction . In Proc. International Symposium on Microarchitecture (MICRO\u201903) . R. Kumar, K. Farkas, N. Jouppi, P. Ranganathan, and D. Tullsen. 2003. Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction. In Proc. International Symposium on Microarchitecture (MICRO\u201903)."},{"key":"e_1_2_1_29_1","volume-title":"Proc. International Symposium on Computer Architecture (MICRO\u201904)","author":"Kumar R.","unstructured":"R. Kumar , D. Tullsen , P. Ranganathan , N. Jouppi , and K. Farkas . 2004. Single-ISA heterogeneous multi-core architectures for multithreaded workload performance . In Proc. International Symposium on Computer Architecture (MICRO\u201904) . R. Kumar, D. Tullsen, P. Ranganathan, N. Jouppi, and K. Farkas. 2004. Single-ISA heterogeneous multi-core architectures for multithreaded workload performance. In Proc. International Symposium on Computer Architecture (MICRO\u201904)."},{"key":"e_1_2_1_30_1","volume-title":"Proc. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS\u201906)","author":"Lee B.","unstructured":"B. Lee and D. Brooks . 2006. Accurate and efficient regression modeling for microarchitectural performance and power prediction . In Proc. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS\u201906) . B. Lee and D. Brooks. 2006. Accurate and efficient regression modeling for microarchitectural performance and power prediction. In Proc. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS\u201906)."},{"key":"e_1_2_1_31_1","volume-title":"Proc. International Symposium on High-Performance Computer Architecture (HPCA\u201907)","author":"Lee B.","unstructured":"B. Lee and D. Brooks . 2007. Illustrative design space studies with microarchitectural regression models . In Proc. International Symposium on High-Performance Computer Architecture (HPCA\u201907) . B. Lee and D. Brooks. 2007. Illustrative design space studies with microarchitectural regression models. In Proc. International Symposium on High-Performance Computer Architecture (HPCA\u201907)."},{"key":"e_1_2_1_32_1","volume-title":"Proc. International Conference on Architectural Support Programming Languages and Operating Systems (ASPLOS\u201908)","author":"Lee B.","unstructured":"B. Lee and D. Brooks . 2008. Efficiency trends and limits from comprehensive microarchitectural activity . In Proc. International Conference on Architectural Support Programming Languages and Operating Systems (ASPLOS\u201908) . B. Lee and D. Brooks. 2008. Efficiency trends and limits from comprehensive microarchitectural activity. In Proc. International Conference on Architectural Support Programming Languages and Operating Systems (ASPLOS\u201908)."},{"key":"e_1_2_1_33_1","volume-title":"Proc. International Symposium on High Performance Computer Architecture (HPCA\u201908)","author":"Lee B.","unstructured":"B. Lee and D. Brooks . 2008. Roughness of microarchitectural design topologies and its implications for optimization . In Proc. International Symposium on High Performance Computer Architecture (HPCA\u201908) . B. Lee and D. Brooks. 2008. Roughness of microarchitectural design topologies and its implications for optimization. In Proc. International Symposium on High Performance Computer Architecture (HPCA\u201908)."},{"key":"e_1_2_1_34_1","volume-title":"Proc. International Conference on Field Programmable Logic and Applications (FPL\u201917)","author":"Liang T.","unstructured":"T. Liang , L. Feng , S. Sinha , and W. Zhang . 2017. PAAS: A system level simulator for heterogeneous computing architectures . In Proc. International Conference on Field Programmable Logic and Applications (FPL\u201917) . T. Liang, L. Feng, S. Sinha, and W. Zhang. 2017. PAAS: A system level simulator for heterogeneous computing architectures. In Proc. International Conference on Field Programmable Logic and Applications (FPL\u201917)."},{"key":"e_1_2_1_35_1","volume-title":"Proc. Design Automation Conference (DAC\u201913)","author":"Liu H.","unstructured":"H. Liu and L. Carloni . 2013. On learning-based methods for design-space exploration with high-level synthesis . In Proc. Design Automation Conference (DAC\u201913) . H. Liu and L. Carloni. 2013. On learning-based methods for design-space exploration with high-level synthesis. In Proc. Design Automation Conference (DAC\u201913)."},{"key":"e_1_2_1_36_1","volume-title":"Proc. International Conference on Frontiers of Information Technology (FIT\u201914)","author":"Liu X.","unstructured":"X. Liu , Xingyu, and Y. Deng . 2014. Fast radix: A scalable hardware accelerator for parallel radix sort . In Proc. International Conference on Frontiers of Information Technology (FIT\u201914) . X. Liu, Xingyu, and Y. Deng. 2014. Fast radix: A scalable hardware accelerator for parallel radix sort. In Proc. International Conference on Frontiers of Information Technology (FIT\u201914)."},{"key":"e_1_2_1_37_1","volume-title":"Proc. International Conference on Field Programmable Logic and Applications (FPL\u201916)","author":"Lo C.","unstructured":"C. Lo and P. Chow . 2016. Model-based optimization of high level synthesis directives . In Proc. International Conference on Field Programmable Logic and Applications (FPL\u201916) . C. Lo and P. Chow. 2016. Model-based optimization of high level synthesis directives. In Proc. International Conference on Field Programmable Logic and Applications (FPL\u201916)."},{"key":"e_1_2_1_38_1","volume-title":"Proc. Electronic System Level Synthesis Conference (ESLsyn\u201914)","author":"Mahapatra A.","unstructured":"A. Mahapatra and B. Schafer . 2014. Machine-learning based simulated annealer method for high level synthesis design space exploration . In Proc. Electronic System Level Synthesis Conference (ESLsyn\u201914) . A. Mahapatra and B. Schafer. 2014. Machine-learning based simulated annealer method for high level synthesis design space exploration. In Proc. Electronic System Level Synthesis Conference (ESLsyn\u201914)."},{"key":"e_1_2_1_39_1","volume-title":"Prospector: Synthesizing efficient accelerators via statistical learning. In 2020 Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201920)","author":"Mehrabi A.","year":"2020","unstructured":"A. Mehrabi , A. Manocha , B. Lee , and D. Sorin . 2020 . Prospector: Synthesizing efficient accelerators via statistical learning. In 2020 Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201920) . IEEE , 151--156. A. Mehrabi, A. Manocha, B. Lee, and D. Sorin. 2020. Prospector: Synthesizing efficient accelerators via statistical learning. In 2020 Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201920). IEEE, 151--156."},{"key":"e_1_2_1_40_1","volume-title":"Proc. International Symposium on Performance Analysis of Systems and Software (ISPASS\u201912)","author":"Meisner D.","unstructured":"D. Meisner , J. Wu , and T. Wenisch . 2012. BigHouse: A simulation infrastructure for data center systems . In Proc. International Symposium on Performance Analysis of Systems and Software (ISPASS\u201912) . D. Meisner, J. Wu, and T. Wenisch. 2012. BigHouse: A simulation infrastructure for data center systems. In Proc. International Symposium on Performance Analysis of Systems and Software (ISPASS\u201912)."},{"key":"e_1_2_1_41_1","doi-asserted-by":"crossref","unstructured":"P. Meng A. Althoff Q. Gautier and R. Kastner. 2016. Adaptive threshold non-pareto elimination: Re-thinking machine learning for system level design space exploration on FPGAs. In 2016 Design Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201916). IEEE 918--923.  P. Meng A. Althoff Q. Gautier and R. Kastner. 2016. Adaptive threshold non-pareto elimination: Re-thinking machine learning for system level design space exploration on FPGAs. In 2016 Design Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201916). IEEE 918--923.","DOI":"10.3850\/9783981537079_0350"},{"key":"e_1_2_1_42_1","volume-title":"Machine Learning: A Probabilistic Approach","author":"Murphy K.","unstructured":"K. Murphy . 2012. Machine Learning: A Probabilistic Approach . MIT Press . K. Murphy. 2012. Machine Learning: A Probabilistic Approach. MIT Press."},{"key":"e_1_2_1_43_1","volume-title":"Proc. International Symposium on Microarchitecture (MICRO\u201916)","author":"Murray S.","unstructured":"S. Murray , W. Floyd-Jones , Y. Qi , G. Konidaris , and D. Sorin . 2016. The microarchitecture of a real-time robot motion planning accelerator . In Proc. International Symposium on Microarchitecture (MICRO\u201916) . S. Murray, W. Floyd-Jones, Y. Qi, G. Konidaris, and D. Sorin. 2016. The microarchitecture of a real-time robot motion planning accelerator. In Proc. International Symposium on Microarchitecture (MICRO\u201916)."},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2513673"},{"key":"e_1_2_1_45_1","unstructured":"Nvidia. 2011. Variable SMP- A multi-core CPU architecture for low power and high performance. Whitepaper. Retrieved from http:\/\/www.nvidia.com.  Nvidia. 2011. Variable SMP- A multi-core CPU architecture for low power and high performance. Whitepaper. Retrieved from http:\/\/www.nvidia.com."},{"key":"e_1_2_1_46_1","volume-title":"Proc. 10th International Symposium on Hardware\/software Codesign. ACM, 67--72","author":"Palesi M.","unstructured":"M. Palesi and T. Givargis . 2002. Multi-objective design space exploration using genetic algorithms . In Proc. 10th International Symposium on Hardware\/software Codesign. ACM, 67--72 . M. Palesi and T. Givargis. 2002. Multi-objective design space exploration using genetic algorithms. In Proc. 10th International Symposium on Hardware\/software Codesign. ACM, 67--72."},{"key":"e_1_2_1_47_1","volume-title":"Proc. International Conference on Hardware\/Software Codesign and System Synthesis.","author":"Pilato C.","unstructured":"C. Pilato , P. Mantovani , G. DiGuglielmo , and L. Carloni . 2014. System-level memory optimization for high-level synthesis of component-based SoCs . In Proc. International Conference on Hardware\/Software Codesign and System Synthesis. C. Pilato, P. Mantovani, G. DiGuglielmo, and L. Carloni. 2014. System-level memory optimization for high-level synthesis of component-based SoCs. In Proc. International Conference on Hardware\/Software Codesign and System Synthesis."},{"key":"e_1_2_1_48_1","volume-title":"Polybench: The polyhedral benchmark suite.","author":"Pouchet L.","year":"2012","unstructured":"L. Pouchet . 2012 . Polybench: The polyhedral benchmark suite. Retrieved from http:\/\/www.cs.ucla. edu\/pouchet\/software\/polybench. L. Pouchet. 2012. Polybench: The polyhedral benchmark suite. Retrieved from http:\/\/www.cs.ucla. edu\/pouchet\/software\/polybench."},{"key":"e_1_2_1_49_1","volume-title":"Proc. International Symposium on Computer Architecuture (ISCA\u201914)","author":"Putnam A.","unstructured":"A. Putnam , A. Caulfield , E. Chung , D. Chiou , and K. Constantinides . 2014. A reconfigurable fabric for accelerating large-scale datacenter services . In Proc. International Symposium on Computer Architecuture (ISCA\u201914) . A. Putnam, A. Caulfield, E. Chung, D. Chiou, and K. Constantinides. 2014. A reconfigurable fabric for accelerating large-scale datacenter services. In Proc. International Symposium on Computer Architecuture (ISCA\u201914)."},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"e_1_2_1_51_1","volume-title":"Proc. International Symposium on Workload Characterization (IISWC\u201914)","author":"Reagen B.","unstructured":"B. Reagen , R. Adolf , Y. Shao , G. Wei , and D. Brooks . 2014. Machsuite: Benchmarks for accelerator design and customized architectures . In Proc. International Symposium on Workload Characterization (IISWC\u201914) . B. Reagen, R. Adolf, Y. Shao, G. Wei, and D. Brooks. 2014. Machsuite: Benchmarks for accelerator design and customized architectures. In Proc. International Symposium on Workload Characterization (IISWC\u201914)."},{"key":"e_1_2_1_52_1","volume-title":"Proc. International Symposium on Low Power Electronics and Design (ISLPED\u201917)","author":"Reagen B.","unstructured":"B. Reagen , J. Hern\u00e1ndez-Lobato , R. Adolf , M. Gelbart , P. Whatmough , G. Wei , and D. Brooks . 2017. A case for efficient accelerator design space exploration via Bayesian optimization . In Proc. International Symposium on Low Power Electronics and Design (ISLPED\u201917) . B. Reagen, J. Hern\u00e1ndez-Lobato, R. Adolf, M. Gelbart, P. Whatmough, G. Wei, and D. Brooks. 2017. A case for efficient accelerator design space exploration via Bayesian optimization. In Proc. International Symposium on Low Power Electronics and Design (ISLPED\u201917)."},{"key":"e_1_2_1_53_1","volume-title":"Proc. International Symposium on Low Power Electronics and Design (ISLPED\u201913)","author":"Reagen B.","unstructured":"B. Reagen , Y. Shao , G. Wei , and D. Brooks . 2013. Quantifying acceleration: Power\/performance trade-offs of application kernels in hardware . In Proc. International Symposium on Low Power Electronics and Design (ISLPED\u201913) . B. Reagen, Y. Shao, G. Wei, and D. Brooks. 2013. Quantifying acceleration: Power\/performance trade-offs of application kernels in hardware. In Proc. International Symposium on Low Power Electronics and Design (ISLPED\u201913)."},{"key":"e_1_2_1_54_1","volume-title":"Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT\u201909)","author":"Schafer B.","unstructured":"B. Schafer , T. Takenaka , and K. Wakabayashi . 2009. Adaptive simulated annealer for high level synthesis design space exploration . In Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT\u201909) . B. Schafer, T. Takenaka, and K. Wakabayashi. 2009. Adaptive simulated annealer for high level synthesis design space exploration. In Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT\u201909)."},{"key":"e_1_2_1_55_1","doi-asserted-by":"crossref","unstructured":"B. Schafer and K. Wakabayashi. 2012. Machine learning predictive modelling high-level synthesis design space exploration. IET Computers 8 Digital Techniques 6 3 (2012) 153--159.  B. Schafer and K. Wakabayashi. 2012. Machine learning predictive modelling high-level synthesis design space exploration. IET Computers 8 Digital Techniques 6 3 (2012) 153--159.","DOI":"10.1049\/iet-cdt.2011.0115"},{"key":"e_1_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2494218"},{"key":"e_1_2_1_57_1","volume-title":"Proc. International Symposium on Computer Architecture (ISCA\u201914)","author":"Shao Y.","unstructured":"Y. Shao , B. Reagen , G. Wei , and D. Brooks . 2014. Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures . In Proc. International Symposium on Computer Architecture (ISCA\u201914) . Y. Shao, B. Reagen, G. Wei, and D. Brooks. 2014. Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures. In Proc. International Symposium on Computer Architecture (ISCA\u201914)."},{"key":"e_1_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2007.904345"},{"key":"e_1_2_1_59_1","volume-title":"Proc. Advances in Neural Information Processing Systems (NIPS\u201912)","author":"Snoek J.","unstructured":"J. Snoek , H. Larochelle , and R. Adams . 2012. Practical Bayesian optimization of machine learning algorithms . In Proc. Advances in Neural Information Processing Systems (NIPS\u201912) . J. Snoek, H. Larochelle, and R. Adams. 2012. Practical Bayesian optimization of machine learning algorithms. In Proc. Advances in Neural Information Processing Systems (NIPS\u201912)."},{"key":"e_1_2_1_60_1","volume-title":"Verilator: Open simulation-growing up. DVClub Bristol.","author":"Snyder W.","year":"2013","unstructured":"W. Snyder . 2013 . Verilator: Open simulation-growing up. DVClub Bristol. W. Snyder. 2013. Verilator: Open simulation-growing up. DVClub Bristol."},{"key":"e_1_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2014.2380198"},{"key":"e_1_2_1_62_1","volume-title":"Proc. Conference on Design, Automation and Test in Europe-Volume 1. IEEE Computer Society, 10318","author":"Szymanek R.","unstructured":"R. Szymanek , F. Catthoor , and K. Kuchcinski . 2004. Time-energy design space exploration for multi-layer memory architectures . In Proc. Conference on Design, Automation and Test in Europe-Volume 1. IEEE Computer Society, 10318 . R. Szymanek, F. Catthoor, and K. Kuchcinski. 2004. Time-energy design space exploration for multi-layer memory architectures. In Proc. Conference on Design, Automation and Test in Europe-Volume 1. IEEE Computer Society, 10318."},{"key":"e_1_2_1_63_1","first-page":"513","article-title":"DLAU: A scalable deep learning accelerator unit on FPGA","volume":"36","author":"Wang C.","year":"2016","unstructured":"C. Wang , L. Gong , Q. Yu , X. Li , Y. Xie , and X. Zhou . 2016 . DLAU: A scalable deep learning accelerator unit on FPGA . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36 , 3 (2016), 513 -- 517 . C. Wang, L. Gong, Q. Yu, X. Li, Y. Xie, and X. Zhou. 2016. DLAU: A scalable deep learning accelerator unit on FPGA. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, 3 (2016), 513--517.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2817118"},{"key":"e_1_2_1_65_1","volume-title":"Proc. International Conference on Field-Programmable Technology (FPT\u201913)","author":"Winterstein F.","unstructured":"F. Winterstein , S. Bayliss , and G. Constantinides . 2013. High-level synthesis of dynamic data structures: A case study using Vivado HLS . In Proc. International Conference on Field-Programmable Technology (FPT\u201913) . F. Winterstein, S. Bayliss, and G. Constantinides. 2013. High-level synthesis of dynamic data structures: A case study using Vivado HLS. In Proc. International Conference on Field-Programmable Technology (FPT\u201913)."},{"key":"e_1_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2363392"},{"key":"e_1_2_1_67_1","volume-title":"Proc. 36th International Conference on Computer-Aided Design.","author":"Zhao J.","unstructured":"J. Zhao , L. Feng , S. Sinha , W. Zhang , Y. Liang , and B. He . 2017. COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications . In Proc. 36th International Conference on Computer-Aided Design. J. Zhao, L. Feng, S. Sinha, W. Zhang, Y. Liang, and B. He. 2017. COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. In Proc. 36th International Conference on Computer-Aided Design."},{"key":"e_1_2_1_68_1","volume-title":"Proc. 53rd Annual Design Automation Conference. ACM, 136","author":"Zhong G.","unstructured":"G. Zhong , A. Prakash , Y. Liang , T. Mitra , and S. Niar . 2016. Lin-analyzer: A high-level performance analysis tool for FPGA-based accelerators . In Proc. 53rd Annual Design Automation Conference. ACM, 136 . G. Zhong, A. Prakash, Y. Liang, T. Mitra, and S. Niar. 2016. Lin-analyzer: A high-level performance analysis tool for FPGA-based accelerators. In Proc. 53rd Annual Design Automation Conference. ACM, 136."}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3427377","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3427377","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:02:26Z","timestamp":1750197746000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3427377"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,12,30]]},"references-count":68,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2021,3,31]]}},"alternative-id":["10.1145\/3427377"],"URL":"https:\/\/doi.org\/10.1145\/3427377","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,12,30]]},"assertion":[{"value":"2020-02-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-12-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}