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Syst."],"published-print":{"date-parts":[[2021,5,31]]},"abstract":"<jats:p>With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This article presents a very low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65 nm technology. Fault simulations performed at the transistor and system-level show that the majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.<\/jats:p>","DOI":"10.1145\/3427911","type":"journal-article","created":{"date-parts":[[2021,1,8]],"date-time":"2021-01-08T12:34:23Z","timestamp":1610109263000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Fault-based Built-in Self-test and Evaluation of Phase Locked Loops"],"prefix":"10.1145","volume":"26","author":[{"given":"Mehmet","family":"Ince","sequence":"first","affiliation":[{"name":"Arizona State University, Tempe, AZ"}]},{"given":"Ender","family":"Yilmaz","sequence":"additional","affiliation":[{"name":"Western Digital Corp., San Jose, CA"}]},{"given":"Wei","family":"Fu","sequence":"additional","affiliation":[{"name":"Texas Instruments, Dallas, TX"}]},{"given":"Joonsung","family":"Park","sequence":"additional","affiliation":[{"name":"Arizona State University, Dallas, TX"}]},{"given":"Krishnaswamy","family":"Nagaraj","sequence":"additional","affiliation":[{"name":"Arizona State University, Dallas, TX"}]},{"given":"Leroy","family":"Winemberg","sequence":"additional","affiliation":[{"name":"Intel Corp., Hillsboro, OR"}]},{"given":"Sule","family":"Ozev","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ"}]}],"member":"320","published-online":{"date-parts":[[2021,1,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.917578"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1173054"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2009.2020588"},{"volume-title":"Proceedings of the IEEE 33rd VLSI Test Symposium (VTS\u201915)","author":"Beohar N.","key":"e_1_2_1_4_1"},{"volume-title":"Proceedings of the Asian Test Symposium. 379--384","author":"Chao A.","key":"e_1_2_1_5_1"},{"volume-title":"Proceedings of the 6th Asian Test Symposium (ATS\u201997)","author":"Dalmia M.","key":"e_1_2_1_6_1"},{"volume-title":"Analog Behavioral Modeling with the Verilog-A Language","author":"Miller Ira","key":"e_1_2_1_7_1"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2005.847343"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2007.910109"},{"volume-title":"Proceedings of the IEEE International Test Conference (ITC\u201907)","author":"Jeong J. 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