{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:20:55Z","timestamp":1750220455304,"version":"3.41.0"},"reference-count":50,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2021,1,4]],"date-time":"2021-01-04T00:00:00Z","timestamp":1609718400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2021,3,31]]},"abstract":"<jats:p>General-purpose computing using graphics processing units (GPGPUs) is an attractive option for acceleration of applications with massively data-parallel tasks. While performance of modern GPGPUs is increasing rapidly, the power consumption of these devices is becoming a major concern. In particular, execution units and register file are among the top three most power-hungry components in GPGPUs. In this work, we exploit trivial instructions to reduce power consumption in GPGPUs.<\/jats:p>\n          <jats:p>Trivial instructions are those instructions that do not need computations, i.e., multiplication by one. We found that, during the course of a program's execution, a GPGPU executes many trivial instructions. Execution of these instructions wastes power unnecessarily. In this work, we propose trivial bypassing which skips execution of trivial instructions and avoids unnecessary allocation of resources for trivial instructions. By power gating execution units and skipping trivial computing, trivial bypassing reduces both static and dynamic power. Also, trivial bypassing reduces dynamic energy of register file by avoiding access to register file for source and\/or destination operands of trivial instructions. While trivial bypassing reduces energy of GPGPUs, it has detrimental impact on performance as a power-gated execution unit requires several cycles to resume its normal operation. Conventional warp schedulers are oblivious to the status of execution units. We propose a new warp scheduler that prioritizes warps based on availability of execution units. We also propose a set of new power management techniques to reduce performance penalty of power gating, further. To increase energy saving of trivial bypassing, we also propose approximating operands of instructions. We offer a set of new techniques to approximate both integer and floating-point instructions and increase the pool of trivial instructions. Our evaluations using a diverse set of benchmarks reveal that our proposed techniques are able to reduce energy of execution units by 11.2% and dynamic energy of register file by 12.2% with minimal performance and quality degradation.<\/jats:p>","DOI":"10.1145\/3429440","type":"journal-article","created":{"date-parts":[[2021,1,4]],"date-time":"2021-01-04T14:49:48Z","timestamp":1609771788000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Reducing Energy in GPGPUs through Approximate Trivial Bypassing"],"prefix":"10.1145","volume":"20","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1662-5334","authenticated-orcid":false,"given":"Ehsan","family":"Atoofian","sequence":"first","affiliation":[{"name":"Lakehead University, Thunder Bay, Ontario, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zayan","family":"Shaikh","sequence":"additional","affiliation":[{"name":"Iowa State University, Ames, Iowa"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ali","family":"Jannesari","sequence":"additional","affiliation":[{"name":"Iowa State University, Ames, Iowa"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2021,1,4]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056031"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/139669.139709"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2025113.2025133"},{"key":"e_1_2_1_4_1","volume-title":"Chilimbi","author":"Baek Woongki","year":"2010","unstructured":"Woongki Baek and Trishul M . Chilimbi . 2010 . Green : A framework for supporting energy-conscious programming using controlled approximation. ACM SIGPLAN Notices 45. ACM , 198--209. Woongki Baek and Trishul M. Chilimbi. 2010. Green: A framework for supporting energy-conscious programming using controlled approximation. ACM SIGPLAN Notices 45. ACM, 198--209."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2002.1106814"},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the 20th Annual International Symposium on Computer Architecture (ISCA'93)","author":"Richardson S.","year":"1993","unstructured":"S. Richardson . 1993 . Caching function results: Faster arithmetic by avoiding unnecessary computation . In Proceedings of the 20th Annual International Symposium on Computer Architecture (ISCA'93) . S. Richardson. 1993. Caching function results: Faster arithmetic by avoiding unnecessary computation. In Proceedings of the 20th Annual International Symposium on Computer Architecture (ISCA'93)."},{"key":"e_1_2_1_7_1","unstructured":"P. Rogers. 2010. CUDA-samples\/Sobel. 2010. github.com\/hellopatrick\/cuda-samples\/tree\/master\/sobel.  P. Rogers. 2010. CUDA-samples\/Sobel. 2010. github.com\/hellopatrick\/cuda-samples\/tree\/master\/sobel."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485951"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"e_1_2_1_10_1","unstructured":"NVIDIA Tesla P100 images.nvidia.com\/content\/pdf\/tesla\/whitepaper\/pascal-architecture-whitepaper.pdf.  NVIDIA Tesla P100 images.nvidia.com\/content\/pdf\/tesla\/whitepaper\/pascal-architecture-whitepaper.pdf."},{"key":"e_1_2_1_11_1","unstructured":"Whitepaper: NVIDIA GeForce GTX 980.  Whitepaper: NVIDIA GeForce GTX 980."},{"key":"e_1_2_1_12_1","volume-title":"Haswell: The fourth-generation Intel core processor","author":"Hammarlund Per","year":"2014","unstructured":"Per Hammarlund , Alberto J. Martinez , Atiq A. Bajwa , David L. Hill , Erik G. Hallnor , Hong Jiang , Martin G. Dixon , Michael Derr , Mikal Hunsaker , Rajesh Kumar , Randy B. Osborne , Ravi Rajwar , Ronak Singhal , Reynold D'Sa , Robert Chappell , Shiv Kaushik , Srinivas Chennupaty , St\u00e9phan Jourdan , Steve Gunther , Thomas Piazza , and Ted Burton . 2014 . Haswell: The fourth-generation Intel core processor . IEEE Micro 34, 2, (2014). Per Hammarlund, Alberto J. Martinez, Atiq A. Bajwa, David L. Hill, Erik G. Hallnor, Hong Jiang, Martin G. Dixon, Michael Derr, Mikal Hunsaker, Rajesh Kumar, Randy B. Osborne, Ravi Rajwar, Ronak Singhal, Reynold D'Sa, Robert Chappell, Shiv Kaushik, Srinivas Chennupaty, St\u00e9phan Jourdan, Steve Gunther, Thomas Piazza, and Ted Burton. 2014. Haswell: The fourth-generation Intel core processor. IEEE Micro 34, 2, (2014)."},{"key":"e_1_2_1_13_1","unstructured":"NVIDIA CUDA C Programming Guide.  NVIDIA CUDA C Programming Guide."},{"key":"e_1_2_1_14_1","volume-title":"Introduction to OpenCL\u2122 Programming","author":"AMD","year":"2010","unstructured":"AMD , Introduction to OpenCL\u2122 Programming . 2010 . AMD, Introduction to OpenCL\u2122 Programming. 2010."},{"key":"e_1_2_1_15_1","volume-title":"NVIDIA's Next Generation CUDA Compute Architecture: Fermi","author":"NVIDIA Corp.","year":"2009","unstructured":"NVIDIA Corp. NVIDIA's Next Generation CUDA Compute Architecture: Fermi , 2009 . NVIDIA Corp. NVIDIA's Next Generation CUDA Compute Architecture: Fermi, 2009."},{"key":"e_1_2_1_16_1","volume-title":"Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software","author":"Bakhoda A.","year":"2009","unstructured":"A. Bakhoda , G. Yuan , W. Fung , H. Wong , and T. Aamodt . 2009. Analyzing CUDA workloads using a detailed GPU simulator . In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software 2009 , 163--174. A. Bakhoda, G. Yuan, W. Fung, H. Wong, and T. Aamodt. 2009. Analyzing CUDA workloads using a detailed GPU simulator. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software 2009, 163--174."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20050084"},{"key":"e_1_2_1_18_1","volume-title":"IISWC","author":"Che S.","year":"2009","unstructured":"S. Che , M. Boyer , J. Meng , D. Tarjan , J. Sheaffer , S.-H. Lee , and K. Skadron . 2009. Rodinia: A benchmark suite for heterogeneous computing . In IISWC , 2009 . S. Che, M. Boyer, J. Meng, D. Tarjan, J. Sheaffer, S.-H. Lee, and K. Skadron. 2009. Rodinia: A benchmark suite for heterogeneous computing. In IISWC, 2009."},{"key":"e_1_2_1_19_1","volume-title":"NVIDIA's Next Generation CUDA Compute Architecture: Kepler GK110","author":"NVIDIA Corp.","year":"2012","unstructured":"NVIDIA Corp. NVIDIA's Next Generation CUDA Compute Architecture: Kepler GK110 , 2012 . NVIDIA Corp. NVIDIA's Next Generation CUDA Compute Architecture: Kepler GK110, 2012."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540719"},{"key":"e_1_2_1_21_1","volume-title":"John Gantz and John Rydning","author":"Reinsel David","year":"2017","unstructured":"David Reinsel , John Gantz and John Rydning . 2017 . Data Age 2025: The Evolution of Data to Life-Critical. International Data Corporation 2017. David Reinsel, John Gantz and John Rydning. 2017. Data Age 2025: The Evolution of Data to Life-Critical. International Data Corporation 2017."},{"volume-title":"Proceedings of the 42nd Annual International Symposium on Computer Architecture (ISCA'15)","author":"Lee S.","key":"e_1_2_1_22_1","unstructured":"S. Lee , K. Kim , G. Koo , H. Jeon , W. W. Ro , and M. Annavaram . 2015. Warped-compression: Enabling power efficient GPUs through register compression . In Proceedings of the 42nd Annual International Symposium on Computer Architecture (ISCA'15) . S. Lee, K. Kim, G. Koo, H. Jeon, W. W. Ro, and M. Annavaram. 2015. Warped-compression: Enabling power efficient GPUs through register compression. In Proceedings of the 42nd Annual International Symposium on Computer Architecture (ISCA'15)."},{"key":"e_1_2_1_23_1","unstructured":"Extracting value from chaos. 2011. www.emc.com\/collateral\/analyst-reports\/idc-extracting-value-from-chaos-ar.pdf.  Extracting value from chaos. 2011. www.emc.com\/collateral\/analyst-reports\/idc-extracting-value-from-chaos-ar.pdf."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155656"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.48"},{"volume-title":"Proceedings of the 24th Annual International Symposium on Computer Architecture (ISCA'97)","author":"Sodani A.","key":"e_1_2_1_26_1","unstructured":"A. Sodani and G. S. Sohi . 1997. Dynamic instruction reuse . Proceedings of the 24th Annual International Symposium on Computer Architecture (ISCA'97) , 194--205. A. Sodani and G. S. Sohi. 1997. Dynamic instruction reuse. Proceedings of the 24th Annual International Symposium on Computer Architecture (ISCA'97), 194--205."},{"key":"e_1_2_1_27_1","volume-title":"AMD","author":"Graphics Cores AMD","year":"2012","unstructured":"AMD Graphics Cores Next (GCN) Architecture . Technical report , AMD , 2012 . AMD Graphics Cores Next (GCN) Architecture. Technical report, AMD, 2012."},{"key":"e_1_2_1_28_1","unstructured":"America's Data Centers Consuming and Wasting Growing Amounts of Energy NRDC. 2015 http:\/\/www.nrdc.org\/energy\/data-center-efficiency-assessment.asp.  America's Data Centers Consuming and Wasting Growing Amounts of Energy NRDC. 2015 http:\/\/www.nrdc.org\/energy\/data-center-efficiency-assessment.asp."},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00041"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485964"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_2_1_32_1","volume-title":"Proceedings of MICRO, 3--14","author":"Muralimanohar Naveen","year":"2007","unstructured":"Naveen Muralimanohar , Rajeev Balasubramonian , and Norman P. Jouppi . 2007. Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0 . In Proceedings of MICRO, 3--14 , 2007 . Naveen Muralimanohar, Rajeev Balasubramonian, and Norman P. Jouppi. 2007. Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0. In Proceedings of MICRO, 3--14, 2007."},{"key":"e_1_2_1_33_1","unstructured":"FreePDKTM process design kit http:\/\/www.eda.ncsu.edu\/wiki\/FreePDK.  FreePDKTM process design kit http:\/\/www.eda.ncsu.edu\/wiki\/FreePDK."},{"volume-title":"Trivial bypassing in GPGPUs","author":"Atoofian E.","key":"e_1_2_1_34_1","unstructured":"E. Atoofian . Trivial bypassing in GPGPUs . IEEE Embed. Syst. Lett . E. Atoofian. Trivial bypassing in GPGPUs. IEEE Embed. Syst. Lett."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/3387902.3392623"},{"key":"e_1_2_1_36_1","unstructured":"NVIDIA CUDA C\/C++ SDK code samples 2013.  NVIDIA CUDA C\/C++ SDK code samples 2013."},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454152"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013249"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628105"},{"key":"e_1_2_1_40_1","volume-title":"Hajar Falahati, Rachata Ausavarungnirun, Arash Tavakkol, Mojtaba Abaee, Lois Orosa, Yaohua Wang, Hamid Sarbazi-Azad, and Onur Mutlu.","author":"Sadrosadati Mohammad","year":"2019","unstructured":"Mohammad Sadrosadati , Seyed Borna Ehsani , Hajar Falahati, Rachata Ausavarungnirun, Arash Tavakkol, Mojtaba Abaee, Lois Orosa, Yaohua Wang, Hamid Sarbazi-Azad, and Onur Mutlu. 2019 . ITAP : Idle-time-aware power management for GPU execution units. ACM TACO. Mohammad Sadrosadati, Seyed Borna Ehsani, Hajar Falahati, Rachata Ausavarungnirun, Arash Tavakkol, Mojtaba Abaee, Lois Orosa, Yaohua Wang, Hamid Sarbazi-Azad, and Onur Mutlu. 2019. ITAP: Idle-time-aware power management for GPU execution units. ACM TACO."},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/2019608.2019612"},{"key":"e_1_2_1_42_1","doi-asserted-by":"crossref","unstructured":"Mark Gebhart Daniel R. Johnson David Tarjan Stephen W. Keckler William J. Dally Erik Lindholm and Kevin Skadron. Energy-efficient mechanisms for managing thread context in throughput processors. ACM SIGARCH Computer Architecture News 39. ACM 235--246.  Mark Gebhart Daniel R. Johnson David Tarjan Stephen W. Keckler William J. Dally Erik Lindholm and Kevin Skadron. Energy-efficient mechanisms for managing thread context in throughput processors. ACM SIGARCH Computer Architecture News 39. ACM 235--246.","DOI":"10.1145\/2024723.2000093"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934606"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/2836168"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.16"},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/3407904"},{"volume-title":"Proceedings of the 48th International Symposium on Microarchitecture (MICRO'15)","author":"Miguel Joshua San","key":"e_1_2_1_47_1","unstructured":"Joshua San Miguel , Jorge Albericio , Andreas Moshovos , and Natalie D . Enright Jerger. 2015. Doppelganger: A cache for approximate computing . In Proceedings of the 48th International Symposium on Microarchitecture (MICRO'15) , (Waikiki, Hawaii). Joshua San Miguel, Jorge Albericio, Andreas Moshovos, and Natalie D. Enright Jerger. 2015. Doppelganger: A cache for approximate computing. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO'15), (Waikiki, Hawaii)."},{"key":"e_1_2_1_48_1","volume-title":"Proceedings of the 46th International Symposium on Microarchitecture, (MICRO'13)","author":"Samadi M.","year":"2013","unstructured":"M. Samadi , J. Lee , D. A. Jamshidi , A. Hormati , and S. Mahlke . 2013. SAGE: Self-tuning approximation for graphics engines . In Proceedings of the 46th International Symposium on Microarchitecture, (MICRO'13) 2013 . M. Samadi, J. Lee, D. A. Jamshidi, A. Hormati, and S. Mahlke. 2013. SAGE: Self-tuning approximation for graphics engines. In Proceedings of the 46th International Symposium on Microarchitecture, (MICRO'13) 2013."},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.30"},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2776272"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3429440","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3429440","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:48:03Z","timestamp":1750193283000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3429440"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1,4]]},"references-count":50,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2021,3,31]]}},"alternative-id":["10.1145\/3429440"],"URL":"https:\/\/doi.org\/10.1145\/3429440","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2021,1,4]]},"assertion":[{"value":"2020-06-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-10-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-01-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}