{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T13:05:48Z","timestamp":1777640748598,"version":"3.51.4"},"reference-count":33,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2020,12,30]],"date-time":"2020-12-30T00:00:00Z","timestamp":1609286400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"crossref","award":["146371743"],"award-info":[{"award-number":["146371743"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2021,3,31]]},"abstract":"<jats:p>Exhaustive verification techniques do not scale with the complexity of today\u2019s multi-tile Multi-processor Systems-on-chip\u00a0(MPSoCs). Hence, runtime verification (RV) has emerged as a complementary method, which verifies the correct behavior of applications executed on the MPSoC during runtime.<\/jats:p>\n          <jats:p>In this article, we propose a decentralized monitoring architecture for large-scale multi-tile MPSoCs. In order to minimize performance and power overhead for RV, we propose a lightweight and non-intrusive hardware solution. It features a new specialized tracing interconnect that distributes and sorts detected events according to their timestamps. Each tile monitor has a consistent view on a globally sorted trace of events on which the behavior of the target application can be verified using logical and timing requirements. Furthermore, we propose an integer linear programming-based algorithm for the assignment of requirements to monitors to exploit the local resources best. The monitoring architecture is demonstrated for a four-tiled MPSoC with 20 cores implemented on a Virtex-7 field-programmable gate array (FPGA).<\/jats:p>","DOI":"10.1145\/3430699","type":"journal-article","created":{"date-parts":[[2020,12,30]],"date-time":"2020-12-30T12:30:51Z","timestamp":1609331451000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs"],"prefix":"10.1145","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7183-485X","authenticated-orcid":false,"given":"Marcel","family":"Mettler","sequence":"first","affiliation":[{"name":"Chair of EDA, Technical University of Munich"}]},{"given":"Daniel","family":"Mueller-Gritschneder","sequence":"additional","affiliation":[{"name":"Chair of EDA, Technical University of Munich"}]},{"given":"Ulf","family":"Schlichtmann","sequence":"additional","affiliation":[{"name":"Chair of EDA, Technical University of Munich"}]}],"member":"320","published-online":{"date-parts":[[2020,12,30]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"AUTOSAR. 2016. Overview of Functional Safety Measures in AUT  AUTOSAR. 2016. Overview of Functional Safety Measures in AUT"},{"key":"e_1_2_1_2_1","unstructured":"ARM. [n.d.]. CoreSight. Retrieved from https:\/\/www.arm.com\/products\/silicon-ip-system.  ARM. [n.d.]. CoreSight. Retrieved from https:\/\/www.arm.com\/products\/silicon-ip-system."},{"key":"e_1_2_1_3_1","unstructured":"S. Bach. 2008. Design and Implementation of a Debugging Unit for the OpenProcessor Platform. Seminar Paper.  S. Bach. 2008. Design and Implementation of a Debugging Unit for the OpenProcessor Platform. Seminar Paper."},{"key":"e_1_2_1_4_1","volume-title":"International Journal of High Performance Computing Applications 5 (Sept.","author":"\u00a0al D. Bailey","year":"1991","unstructured":"D. Bailey et \u00a0al . 1991. The Nas parallel benchmarks . International Journal of High Performance Computing Applications 5 (Sept. 1991 ), 63--73. D. Bailey et\u00a0al. 1991. The Nas parallel benchmarks. International Journal of High Performance Computing Applications 5 (Sept. 1991), 63--73."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000799.2000800"},{"key":"e_1_2_1_6_1","doi-asserted-by":"crossref","unstructured":"J. O. Blech Y. Falcone and K. Becker. 2012. Towards certified runtime verification. In Formal Methods and Software Engineering Toshiaki Aoki and Kenji Taguchi (Eds.). Springer Berlin 494--509.  J. O. Blech Y. Falcone and K. Becker. 2012. Towards certified runtime verification. In Formal Methods and Software Engineering Toshiaki Aoki and Kenji Taguchi (Eds.). Springer Berlin 494--509.","DOI":"10.1007\/978-3-642-34281-3_34"},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the 2018 Design, Automation Test in Europe Conference Exhibition (DATE). 851--856","author":"\u00a0al N. Decker","year":"2018","unstructured":"N. Decker et \u00a0al . 2018 . Online analysis of debug trace data for embedded systems . In Proceedings of the 2018 Design, Automation Test in Europe Conference Exhibition (DATE). 851--856 . N. Decker et\u00a0al. 2018. Online analysis of debug trace data for embedded systems. In Proceedings of the 2018 Design, Automation Test in Europe Conference Exhibition (DATE). 851--856."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2014.8"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2010.2068304"},{"key":"e_1_2_1_10_1","volume-title":"A foundation for runtime monitoring","author":"\u00a0al A. Francalanza","unstructured":"A. Francalanza et \u00a0al . 2017. A foundation for runtime monitoring . In Runtime Verification, Shuvendu Lahiri and Giles Reger (Eds.). Springer International Publishing , Cham , 8--29. A. Francalanza et\u00a0al. 2017. A foundation for runtime monitoring. In Runtime Verification, Shuvendu Lahiri and Giles Reger (Eds.). Springer International Publishing, Cham, 8--29."},{"key":"e_1_2_1_11_1","volume-title":"Runtime Verification for Decentralised and Distributed Systems","author":"Francalanza A.","unstructured":"A. Francalanza , Jorge A. P\u00e9rez , and C\u00e9sar S\u00e1nchez . 2018. Runtime Verification for Decentralised and Distributed Systems . Springer International Publishing , Cham , 176--210. A. Francalanza, Jorge A. P\u00e9rez, and C\u00e9sar S\u00e1nchez. 2018. Runtime Verification for Decentralised and Distributed Systems. Springer International Publishing, Cham, 176--210."},{"key":"e_1_2_1_12_1","volume-title":"Striver: Stream runtime verification for real-time event-streams","author":"Gorostiaga F.","year":"2018","unstructured":"F. Gorostiaga and C. S\u00e1nchez . 2018 . Striver: Stream runtime verification for real-time event-streams . In Runtime Verification, C. Colombo and M. Leucker (Eds.). Springer International Publishing , Cham , 282--298. F. Gorostiaga and C. S\u00e1nchez. 2018. Striver: Stream runtime verification for real-time event-streams. In Runtime Verification, C. Colombo and M. Leucker (Eds.). Springer International Publishing, Cham, 282--298."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-sen.2013.0236"},{"key":"e_1_2_1_14_1","volume-title":"Andrei Voronkov and Margarita Korovina (Eds.)","volume":"42","author":"Hinrichs T. L.","unstructured":"T. L. Hinrichs , A. Prasad Sistla , and L. D. Zuck . 2014. Model check what you can, runtime verify the rest. In HOWARD-60. A Festschrift on the Occasion of Howard Barringer\u2019s 60th Birthday (EPiC Series in Computing) , Andrei Voronkov and Margarita Korovina (Eds.) , Vol. 42 . EasyChair, 234--244. T. L. Hinrichs, A. Prasad Sistla, and L. D. Zuck. 2014. Model check what you can, runtime verify the rest. In HOWARD-60. A Festschrift on the Occasion of Howard Barringer\u2019s 60th Birthday (EPiC Series in Computing), Andrei Voronkov and Margarita Korovina (Eds.), Vol. 42. EasyChair, 234--244."},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the 2008 International Conference on Field Programmable Logic and Applications. 551--554","author":"Hochberger C.","unstructured":"C. Hochberger and A. Weiss . 2008. A new methodology for debugging and validation of soft cores . In Proceedings of the 2008 International Conference on Field Programmable Logic and Applications. 551--554 . C. Hochberger and A. Weiss. 2008. A new methodology for debugging and validation of soft cores. In Proceedings of the 2008 International Conference on Field Programmable Logic and Applications. 551--554."},{"key":"e_1_2_1_16_1","unstructured":"Institute for Software Engineering and Programming Languages. [n.d.]. LamaConv\u2014Logics and Automata Converter Library. Retrieved from https:\/\/www.isp.uni-luebeck.de\/lamaconv.  Institute for Software Engineering and Programming Languages. [n.d.]. LamaConv\u2014Logics and Automata Converter Library. Retrieved from https:\/\/www.isp.uni-luebeck.de\/lamaconv."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF02107058"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jlap.2008.08.004"},{"key":"e_1_2_1_19_1","volume-title":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). 220--225","author":"Listl A.","unstructured":"A. Listl , D. Mueller-Gritschneder , F. Kluge , and U. Schlichtmann . 2018. Emulation of an ASIC power, temperature and aging monitor system for FPGA prototyping . In 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). 220--225 . A. Listl, D. Mueller-Gritschneder, F. Kluge, and U. Schlichtmann. 2018. Emulation of an ASIC power, temperature and aging monitor system for FPGA prototyping. In 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). 220--225."},{"key":"e_1_2_1_20_1","first-page":"10","article-title":"Automatic processor customization for zero-overhead online software verification","volume":"16","author":"Lu H.","year":"2008","unstructured":"H. Lu and A. Forin . 2008 . Automatic processor customization for zero-overhead online software verification . IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 , 10 (Oct. 2008), 1346--1357. H. Lu and A. Forin. 2008. Automatic processor customization for zero-overhead online software verification. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, 10 (Oct. 2008), 1346--1357.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID49098.2020.00026"},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES). 137--146","author":"Nassar A.","unstructured":"A. Nassar , F. J. Kurdahi , and W. Elsharkasy . 2015. NUVA: Architectural support for runtime verification of parametric specifications over multicores . In Proceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES). 137--146 . A. Nassar, F. J. Kurdahi, and W. Elsharkasy. 2015. NUVA: Architectural support for runtime verification of parametric specifications over multicores. In Proceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES). 137--146."},{"key":"e_1_2_1_23_1","volume-title":"Proceedings of the 1990 International Conference on Parallel Processing. 93--97","author":"Netzer R. H. B.","unstructured":"R. H. B. Netzer and B. P. Miller . 1990. On the complexity of event ordering for shared-memory parallel program executions . In Proceedings of the 1990 International Conference on Parallel Processing. 93--97 . R. H. B. Netzer and B. P. Miller. 1990. On the complexity of event ordering for shared-memory parallel program executions. In Proceedings of the 1990 International Conference on Parallel Processing. 93--97."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2009.08.006"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5120\/1343-1448"},{"key":"e_1_2_1_26_1","volume-title":"Proceedings of the 2012 IEEE\/ASME 8th IEEE\/ASME International Conference on Mechatronic and Embedded Systems and Applications. 224--231","author":"Reinbacher T.","unstructured":"T. Reinbacher , J. Geist , P. Moosbrugger , M. Horauer , and A. Steininger . 2012. Parallel runtime verification of temporal properties for embedded software . In Proceedings of the 2012 IEEE\/ASME 8th IEEE\/ASME International Conference on Mechatronic and Embedded Systems and Applications. 224--231 . T. Reinbacher, J. Geist, P. Moosbrugger, M. Horauer, and A. Steininger. 2012. Parallel runtime verification of temporal properties for embedded software. In Proceedings of the 2012 IEEE\/ASME 8th IEEE\/ASME International Conference on Mechatronic and Embedded Systems and Applications. 224--231."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/3358200"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/3206213"},{"key":"e_1_2_1_29_1","volume-title":"Proceedings of the 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES). 1--6.","author":"Solet D.","unstructured":"D. Solet , J. B\u00e9chennec , M. Briday , S. Faucou , and S. Pillement . 2016. Hardware runtime verification of embedded software in SoPC . In Proceedings of the 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES). 1--6. D. Solet, J. B\u00e9chennec, M. Briday, S. Faucou, and S. Pillement. 2016. Hardware runtime verification of embedded software in SoPC. In Proceedings of the 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES). 1--6."},{"key":"e_1_2_1_30_1","volume-title":"Proceedings of the 2018 14th European Dependable Computing Conference (EDCC). 25--32","author":"Solet D.","unstructured":"D. Solet , J. B\u00e9chennec , M. Briday , S. Faucou , and S. Pillement . 2018. Hardware runtime verification of a RTOS kernel: Evaluation using fault injection . In Proceedings of the 2018 14th European Dependable Computing Conference (EDCC). 25--32 . D. Solet, J. B\u00e9chennec, M. Briday, S. Faucou, and S. Pillement. 2018. Hardware runtime verification of a RTOS kernel: Evaluation using fault injection. In Proceedings of the 2018 14th European Dependable Computing Conference (EDCC). 25--32."},{"key":"e_1_2_1_31_1","volume-title":"Proceedings of the 2018 NASA\/ESA Conference on Adaptive Hardware and Systems (AHS). 249--256","author":"Solet D.","unstructured":"D. Solet , S. Pillement , J. B\u00e9chennec , M. Briday , and S. Faucou . 2018. HW-based architecture for runtime verification of embedded software on SoPC systems . In Proceedings of the 2018 NASA\/ESA Conference on Adaptive Hardware and Systems (AHS). 249--256 . D. Solet, S. Pillement, J. B\u00e9chennec, M. Briday, and S. Faucou. 2018. HW-based architecture for runtime verification of embedded software on SoPC systems. In Proceedings of the 2018 NASA\/ESA Conference on Adaptive Hardware and Systems (AHS). 249--256."},{"key":"e_1_2_1_32_1","volume-title":"The Design of a Debugger Unit for a RISC Processor Core. Master\u2019s thesis","author":"Velguenkar N.","unstructured":"N. Velguenkar . 2018. The Design of a Debugger Unit for a RISC Processor Core. Master\u2019s thesis . Rochester Institute of Technology (RIT) . N. Velguenkar. 2018. The Design of a Debugger Unit for a RISC Processor Core. Master\u2019s thesis. Rochester Institute of Technology (RIT)."},{"key":"e_1_2_1_33_1","unstructured":"P. Wagner T. Wild and A. Herkersdorf. 2016. Improving SoC insight through on-chip diagnosis. CoRR abs\/1607.04549 (2016). arxiv:1607.04549  P. Wagner T. Wild and A. Herkersdorf. 2016. Improving SoC insight through on-chip diagnosis. CoRR abs\/1607.04549 (2016). arxiv:1607.04549"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3430699","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3430699","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:24:41Z","timestamp":1750195481000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3430699"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,12,30]]},"references-count":33,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2021,3,31]]}},"alternative-id":["10.1145\/3430699"],"URL":"https:\/\/doi.org\/10.1145\/3430699","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,12,30]]},"assertion":[{"value":"2020-05-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-10-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-12-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}