{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,24]],"date-time":"2026-07-24T04:17:45Z","timestamp":1784866665066,"version":"3.55.0"},"reference-count":46,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2021,1,6]],"date-time":"2021-01-06T00:00:00Z","timestamp":1609891200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000183","name":"Army Research Office","doi-asserted-by":"publisher","award":["W911NF-17-1-0485"],"award-info":[{"award-number":["W911NF-17-1-0485"]}],"id":[{"id":"10.13039\/100000183","id-type":"DOI","asserted-by":"publisher"}]},{"name":"NSF","award":["CNS-1955353, CNS-1564014"],"award-info":[{"award-number":["CNS-1955353, CNS-1564014"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2021,4,30]]},"abstract":"<jats:p>Voltage\/frequency island (VFI)-based power management is a popular methodology for designing energy-efficient manycore architectures without incurring significant performance overhead. However, monolithic 3D (M3D) integration has emerged as an enabling technology to design high-performance and energy-efficient circuits and systems. The smaller dimension of vertical monolithic inter-tier vias (MIVs) lowers effective wirelength and allows high integration density. However, sequential fabrication of M3D layers introduces inter-tier process variations that affect the performance of transistors and interconnects in different layers. Therefore, VFI-based power management in M3D manycore systems requires the consideration of inter-tier process variation effects. In this work, we present the design of an imitation learning (IL)-enabled VFI-based power-management strategy that considers the inter-tier process-variation effects in M3D manycore chips. We demonstrate that the IL-based power-management strategy can be fine-tuned based on the M3D characteristics. Our policy generates suitable V\/F levels based on the computation and communication characteristics of the system for both process-oblivious and process-aware configurations. We show that the proposed process-variation-aware IL-based VFI implementation for M3D manycore chips lowers the overall energy-delay-product (EDP) by up to 16.2% on average compared to an ideal M3D system with no M3D process variations.<\/jats:p>","DOI":"10.1145\/3430765","type":"journal-article","created":{"date-parts":[[2021,1,6]],"date-time":"2021-01-06T17:09:58Z","timestamp":1609952998000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Power Management of Monolithic 3D Manycore Chips with Inter-tier Process Variations"],"prefix":"10.1145","volume":"17","author":[{"given":"Anwesha","family":"Chatterjee","sequence":"first","affiliation":[{"name":"Colorado State University, Fort Collins, Colorado, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shouvik","family":"Musavvir","sequence":"additional","affiliation":[{"name":"Colorado State University, Fort Collins, Colorado, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ryan Gary","family":"Kim","sequence":"additional","affiliation":[{"name":"Colorado State University, Fort Collins, Colorado, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Janardhan Rao","family":"Doppa","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, Washington, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Partha Pratim","family":"Pande","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, Washington, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2021,1,6]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2008.5388567"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2074070"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.125"},{"key":"e_1_2_1_5_1","volume-title":"Proceedings of the Design Automation Conference (DAC\u201913)","author":"Lee Y. J.","unstructured":"Y. J. Lee , D. Limbrick , and S. K. Lim . 2013. Power benefit study for ultra-high density transistor-level monolithic 3D ICs . In Proceedings of the Design Automation Conference (DAC\u201913) . 1--10. Y. J. Lee, D. Limbrick, and S. K. Lim. 2013. Power benefit study for ultra-high density transistor-level monolithic 3D ICs. In Proceedings of the Design Automation Conference (DAC\u201913). 1--10."},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the IEEE International Interconnect Technology Conference (IITC\u201914)","author":"Batude P.","unstructured":"P. Batude , B. Sklenard , C. Fenouillet-Beranger , B. Previtali , C. Tabone , O. Rozeau , O. Billoint , O. Turkyilmaz , H. Sarhan , S. Thuries , G. Cibrario , L. Brunet , F. Deprat , J.-E. Michallet , F. Clermidy , and M. Vinet . 2014. 3D sequential integration opportunities and technology optimization . In Proceedings of the IEEE International Interconnect Technology Conference (IITC\u201914) . 373--376. P. Batude, B. Sklenard, C. Fenouillet-Beranger, B. Previtali, C. Tabone, O. Rozeau, O. Billoint, O. Turkyilmaz, H. Sarhan, S. Thuries, G. Cibrario, L. Brunet, F. Deprat, J.-E. Michallet, F. Clermidy, and M. Vinet. 2014. 3D sequential integration opportunities and technology optimization. In Proceedings of the IEEE International Interconnect Technology Conference (IITC\u201914). 373--376."},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S\u201915)","author":"Nayak D. K.","unstructured":"D. K. Nayak , S. Banna , S. K. Samal , and S. K. Lim . 2015. Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs . In Proceedings of the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S\u201915) . 1--2. D. K. Nayak, S. Banna, S. K. Samal, and S. K. Lim. 2015. Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs. In Proceedings of the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S\u201915). 1--2."},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of the Conference on Design, Automation 8 Test in Europe (DATE\u201914)","author":"Turkyilmaz O.","unstructured":"O. Turkyilmaz , G. Cibrario , O. Rozeau , P. Batude , and F. Clermidy . 2014. 3D FPGA using high-density interconnect monolithic integration . In Proceedings of the Conference on Design, Automation 8 Test in Europe (DATE\u201914) . 1--4. O. Turkyilmaz, G. Cibrario, O. Rozeau, P. Batude, and F. Clermidy. 2014. 3D FPGA using high-density interconnect monolithic integration. In Proceedings of the Conference on Design, Automation 8 Test in Europe (DATE\u201914). 1--4."},{"key":"e_1_2_1_9_1","volume-title":"Proceedings of the IEEE International Conference on Computer Design (ICCD\u201917)","author":"Das S.","unstructured":"S. Das , J. R. Doppa , P. P. Pande , and K. Chakrabarty . 2017. Monolithic 3D-enabled high performance and energy efficient network-on-chip . In Proceedings of the IEEE International Conference on Computer Design (ICCD\u201917) . 233--224. S. Das, J. R. Doppa, P. P. Pande, and K. Chakrabarty. 2017. Monolithic 3D-enabled high performance and energy efficient network-on-chip. In Proceedings of the IEEE International Conference on Computer Design (ICCD\u201917). 233--224."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.891300"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2223593"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2954770"},{"key":"e_1_2_1_13_1","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3223046","article-title":"Performance and thermal tradeoffs for energy-efficient monolithic 3D network-on-chip","volume":"23","author":"Lee D.","year":"2018","unstructured":"D. Lee , S. Das , J. R. Doppa , P. P. Pande , and K. Chakrabarty . 2018 . Performance and thermal tradeoffs for energy-efficient monolithic 3D network-on-chip . ACM Trans. Des. Autom. Electron. Syst. 23 , 5 (2018), 1 -- 25 . D. Lee, S. Das, J. R. Doppa, P. P. Pande, and K. Chakrabarty. 2018. Performance and thermal tradeoffs for energy-efficient monolithic 3D network-on-chip. ACM Trans. Des. Autom. Electron. Syst. 23, 5 (2018), 1--25.","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2491675"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887920"},{"key":"e_1_2_1_16_1","volume-title":"Proceedings of the SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S\u201914)","author":"Uhrmann T.","unstructured":"T. Uhrmann , T. Wagenleitner , T. Glinsner , M. Wimplinger , and P. Lindner . 2014. Monolithic IC integration key alignment aspects for high process yield . In Proceedings of the SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S\u201914) . 1--2. T. Uhrmann, T. Wagenleitner, T. Glinsner, M. Wimplinger, and P. Lindner. 2014. Monolithic IC integration key alignment aspects for high process yield. In Proceedings of the SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S\u201914). 1--2."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2273986"},{"key":"e_1_2_1_18_1","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD\u201912)","author":"Lee Y. J.","unstructured":"Y. J. Lee , P. Morrow , and S. K. Lim . 2012. Ultra high density logic designs using transistor-level monolithic 3D integration . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD\u201912) . 539--546. Y. J. Lee, P. Morrow, and S. K. Lim. 2012. Ultra high density logic designs using transistor-level monolithic 3D integration. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD\u201912). 539--546."},{"key":"e_1_2_1_19_1","volume-title":"Proceedings of the IEEE SOI-3D-Subthreshold Microelectronic Technology Unified Conference (S3S\u201916)","author":"Samal S. K.","unstructured":"S. K. Samal , D. Nayak , M. Ichihashi , S. Banna , and S. K. Lim . 2016. Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology . In Proceedings of the IEEE SOI-3D-Subthreshold Microelectronic Technology Unified Conference (S3S\u201916) . 1--2. S. K. Samal, D. Nayak, M. Ichihashi, S. Banna, and S. K. Lim. 2016. Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology. In Proceedings of the IEEE SOI-3D-Subthreshold Microelectronic Technology Unified Conference (S3S\u201916). 1--2."},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the 17th International Symposium on Quality Electronic Design (ISQED\u201916)","author":"Acharya K.","unstructured":"K. Acharya , K. Chang , B. W. Ku , S. Panth , S. Sinha , B. Cline , G. Yeric , and S. K. Lim . 2016. Monolithic 3D IC design: Power, performance, and area impact at 7nm . In Proceedings of the 17th International Symposium on Quality Electronic Design (ISQED\u201916) . 41--48. K. Acharya, K. Chang, B. W. Ku, S. Panth, S. Sinha, B. Cline, G. Yeric, and S. K. Lim. 2016. Monolithic 3D IC design: Power, performance, and area impact at 7nm. In Proceedings of the 17th International Symposium on Quality Electronic Design (ISQED\u201916). 41--48."},{"key":"e_1_2_1_21_1","volume-title":"Proceedings of the International Symposium on Low Power Electronics and Design. 70--75","author":"Kim K. M.","unstructured":"K. M. Kim , S. Sinha , B. Cline , G. Yeric , and S. K. Lim . 2016. Four-tier monolithic 3D ICs: Tier partitioning methodology and power benefit study . In Proceedings of the International Symposium on Low Power Electronics and Design. 70--75 . K. M. Kim, S. Sinha, B. Cline, G. Yeric, and S. K. Lim. 2016. Four-tier monolithic 3D ICs: Tier partitioning methodology and power benefit study. In Proceedings of the International Symposium on Low Power Electronics and Design. 70--75."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2681064"},{"key":"e_1_2_1_23_1","volume-title":"Proceedings of the SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S\u201914)","author":"Pasini L.","unstructured":"L. Pasini , P. Batude , M. Cass\u00e9 , L. Brunet , P. Rivallin , B. Mathieu , J. Lacord , S. Martinie , C. Fenouillet-Beranger , B. Previtali , N. Rambal , M. Haond , G. Ghibaudo , and M. Vinet . 2014. nFET FDSOI activated by low temperature solid phase epitaxial regrowth: Optimization guidelines . In Proceedings of the SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S\u201914) . 1--2. L. Pasini, P. Batude, M. Cass\u00e9, L. Brunet, P. Rivallin, B. Mathieu, J. Lacord, S. Martinie, C. Fenouillet-Beranger, B. Previtali, N. Rambal, M. Haond, G. Ghibaudo, and M. Vinet. 2014. nFET FDSOI activated by low temperature solid phase epitaxial regrowth: Optimization guidelines. In Proceedings of the SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S\u201914). 1--2."},{"key":"e_1_2_1_24_1","volume-title":"Proceedings of the IEEE International Electron Device Meeting. 27","author":"Fenouillet-Beranger C.","year":"2014","unstructured":"C. Fenouillet-Beranger , B. Mathieu , B. Previtali , M. Samson , N. Rambal , V. Benevent , S. Kerdiles , J. Barnes , D. Barge , P. Besson , R. Kachtouli , M. Cass\u00e9 , X. Garros , A. Laurent , F. Nemouchi , K. Huet , I. Toqu\u00e9-Tr\u00e9sonne , D. Lafond , H. Dansas , F. Aussenac , G. Druais , P. Perreau , E. Richard , S. Chhun , E. Petitprez , N. Guillot , F. Deprat , L. Pasini , L. Brunet , V. Lu , C. Reita , P. Batude , and M. Vinet . 2014. New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI . In Proceedings of the IEEE International Electron Device Meeting. 27 , 5 ( 2014 ) 1--27. C. Fenouillet-Beranger, B. Mathieu, B. Previtali, M. Samson, N. Rambal, V. Benevent, S. Kerdiles, J. Barnes, D. Barge, P. Besson, R. Kachtouli, M. Cass\u00e9, X. Garros, A. Laurent, F. Nemouchi, K. Huet, I. Toqu\u00e9-Tr\u00e9sonne, D. Lafond, H. Dansas, F. Aussenac, G. Druais, P. Perreau, E. Richard, S. Chhun, E. Petitprez, N. Guillot, F. Deprat, L. Pasini, L. Brunet, V. Lu, C. Reita, P. Batude, and M. Vinet. 2014. New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI. In Proceedings of the IEEE International Electron Device Meeting. 27, 5 (2014) 1--27."},{"key":"e_1_2_1_25_1","volume-title":"Proceedings of the 46th International Symposium on Computer Architecture (ISCA\u201919)","author":"Gopireddy B.","unstructured":"B. Gopireddy and J. Torrellas . 2019. Designing vertical processors in monolithic 3D . In Proceedings of the 46th International Symposium on Computer Architecture (ISCA\u201919) . Association for Computing Machinery, 643--656. B. Gopireddy and J. Torrellas. 2019. Designing vertical processors in monolithic 3D. In Proceedings of the 46th International Symposium on Computer Architecture (ISCA\u201919). Association for Computing Machinery, 643--656."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2011229"},{"key":"e_1_2_1_27_1","volume-title":"Proceedings of the IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201913)","author":"Juan D. C.","unstructured":"D. C. Juan , S. Garg , J. Park , and D. Marculescu . 2013. Learning the optimal operating point for many-core systems with extended range voltage\/frequency scaling . In Proceedings of the IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201913) . 1--10. D. C. Juan, S. Garg, J. Park, and D. Marculescu. 2013. Learning the optimal operating point for many-core systems with extended range voltage\/frequency scaling. In Proceedings of the IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201913). 1--10."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2512611"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2018.2878699"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2700726"},{"key":"e_1_2_1_31_1","volume-title":"Proceedings of the Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201915)","author":"Shulaker M. M.","unstructured":"M. M. Shulaker , T. F. Wu , M. M. Sabry , H. Wei , H. P. Wong , and S. Mitra . 2015. Monolithic 3D integration: A path from concept to reality . In Proceedings of the Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201915) . 1197--1202. M. M. Shulaker, T. F. Wu, M. M. Sabry, H. Wei, H. P. Wong, and S. Mitra. 2015. Monolithic 3D integration: A path from concept to reality. In Proceedings of the Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201915). 1197--1202."},{"key":"e_1_2_1_32_1","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD\u201910)","author":"Athikulwongse K.","unstructured":"K. Athikulwongse , A. Chakraborty , J.-S. Yang , D. Z. Pan , and S. K. Lim . 2010. Stress-driven 3D-IC placement with TSV keep-out zone and regularity study . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD\u201910) . 669--674. K. Athikulwongse, A. Chakraborty, J.-S. Yang, D. Z. Pan, and S. K. Lim. 2010. Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD\u201910). 669--674."},{"key":"e_1_2_1_33_1","volume-title":"Proceedings of the International Conference on Artificial Intelligence and Statististics. 627--635","author":"Ross S.","unstructured":"S. Ross , G. J. Gordon , and J. A. Bagnell . 2011. A reduction of imitation learning and structured prediction to no-regret online learning . In Proceedings of the International Conference on Artificial Intelligence and Statististics. 627--635 . S. Ross, G. J. Gordon, and J. A. Bagnell. 2011. A reduction of imitation learning and structured prediction to no-regret online learning. In Proceedings of the International Conference on Artificial Intelligence and Statististics. 627--635."},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_35_1","volume-title":"Proceedings of the International Symposium on Computer Architecture (ISCA\u201995)","author":"Woo S. C.","unstructured":"S. C. Woo , M. Ohara , E. Torrie , J. P. Singh , and A. Gupta . 1995. The SPLASH-2 programs: Characterization and methodological considerations . In Proceedings of the International Symposium on Computer Architecture (ISCA\u201995) . 24--36. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. 1995. The SPLASH-2 programs: Characterization and methodological considerations. In Proceedings of the International Symposium on Computer Architecture (ISCA\u201995). 24--36."},{"key":"e_1_2_1_37_1","volume-title":"Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201909)","author":"Li S.","unstructured":"S. Li , J. H. Ahn , R. D. Strong , J. B. Brockman , D. M. Tullsen , and N. P. Jouppi . 2009. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures . In Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201909) . 469--480. S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi. 2009. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201909). 469--480."},{"key":"e_1_2_1_38_1","volume-title":"Proceedings of the Design, Automation and Test in Europe Conference (DATE\u201917)","author":"Das S.","unstructured":"S. Das , J. R. Doppa , P. P. Pande , and K. Chakrabarty . 2017. Robust TSV-based 3D NoC design to counteract electromigration and crosstalk noise . In Proceedings of the Design, Automation and Test in Europe Conference (DATE\u201917) . 1366--1371. S. Das, J. R. Doppa, P. P. Pande, and K. Chakrabarty. 2017. Robust TSV-based 3D NoC design to counteract electromigration and crosstalk noise. In Proceedings of the Design, Automation and Test in Europe Conference (DATE\u201917). 1366--1371."},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2604288"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2014.2357397"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024774"},{"key":"e_1_2_1_42_1","unstructured":"ITRS Reports. 2015. The International Technology Roadmap for Semiconductors. Retrieved from http:\/\/www.itrs2.net\/itrs-reports.html.  ITRS Reports. 2015. The International Technology Roadmap for Semiconductors. Retrieved from http:\/\/www.itrs2.net\/itrs-reports.html."},{"key":"e_1_2_1_43_1","volume-title":"Proceedings of the IEEE International Symposium on Computer Architecture (ISCA\u201906)","author":"Li F.","unstructured":"F. Li , C. Nicopoulos , T. Richardson , Y. Xie , V. Narayanan , and M. Kandemir . 2006. Design and management of 3D chip multiprocessors using network-in-memory . In Proceedings of the IEEE International Symposium on Computer Architecture (ISCA\u201906) . 130--141. F. Li, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, and M. Kandemir. 2006. Design and management of 3D chip multiprocessors using network-in-memory. In Proceedings of the IEEE International Symposium on Computer Architecture (ISCA\u201906). 130--141."},{"key":"e_1_2_1_44_1","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers. 130--131","author":"Kang U.","unstructured":"U. Kang , H. J. Chung , S. Heo , S. H. Ahn , H. Lee , S. H. Cha , J. Ahn , D. Kwon , J. H. Kim , J. W. Lee , H. S. Joo , W. S. Kim , H. K. Kim , E. M. Lee , S. R. Kim , K. H. Ma , D. H. Jang , N. S. Kim , M. S. Choi , S. J. Oh , J. B. Lee , T. K. Jung , J. H. Yoo , and C. Kim . 2009. 8Gb 3D DDR3 DRAM using through-silicon-via technology . In Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers. 130--131 . U. Kang, H. J. Chung, S. Heo, S. H. Ahn, H. Lee, S. H. Cha, J. Ahn, D. Kwon, J. H. Kim, J. W. Lee, H. S. Joo, W. S. Kim, H. K. Kim, E. M. Lee, S. R. Kim, K. H. Ma, D. H. Jang, N. S. Kim, M. S. Choi, S. J. Oh, J. B. Lee, T. K. Jung, J. H. Yoo, and C. Kim. 2009. 8Gb 3D DDR3 DRAM using through-silicon-via technology. In Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers. 130--131."},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884079"},{"key":"e_1_2_1_46_1","volume-title":"Proceedings of the IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED\u201915)","author":"Rahmani A.","unstructured":"A. Rahmani , M. Haghbayan , A. Kanduri , A. Y. Weldezion , P. Liljeberg , J. Plosila , A. Jantsch , and H. Tenhunen . 2015. Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach . In Proceedings of the IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED\u201915) . 219--224. A. Rahmani, M. Haghbayan, A. Kanduri, A. Y. Weldezion, P. Liljeberg, J. Plosila, A. Jantsch, and H. Tenhunen. 2015. Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach. In Proceedings of the IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED\u201915). 219--224."},{"key":"e_1_2_1_47_1","volume-title":"Proceedings of the 34th International Conference Machine Learning 70","author":"Sun W.","year":"2017","unstructured":"W. Sun , A. Venkatraman , G. J. Gordon , B. Boots , and J. A. Bagnell . 2017. Deeply AggreVaTeD: Differentiable imitation learning for sequential prediction . In Proceedings of the 34th International Conference Machine Learning 70 ( 2017 ), 3309--3318. W. Sun, A. Venkatraman, G. J. Gordon, B. Boots, and J. A. Bagnell. 2017. Deeply AggreVaTeD: Differentiable imitation learning for sequential prediction. In Proceedings of the 34th International Conference Machine Learning 70 (2017), 3309--3318."}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3430765","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3430765","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3430765","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:24:41Z","timestamp":1750195481000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3430765"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1,6]]},"references-count":46,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2021,4,30]]}},"alternative-id":["10.1145\/3430765"],"URL":"https:\/\/doi.org\/10.1145\/3430765","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"value":"1550-4832","type":"print"},{"value":"1550-4840","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,1,6]]},"assertion":[{"value":"2020-05-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-10-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-01-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}