{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T07:04:01Z","timestamp":1777100641374,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":69,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,2,17]],"date-time":"2021-02-17T00:00:00Z","timestamp":1613520000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000002","name":"NIH (National Institutes of Health)","doi-asserted-by":"publisher","award":["U01MH117079"],"award-info":[{"award-number":["U01MH117079"]}],"id":[{"id":"10.13039\/100000002","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["DBI-1707408"],"award-info":[{"award-number":["DBI-1707408"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,2,17]]},"DOI":"10.1145\/3431920.3439289","type":"proceedings-article","created":{"date-parts":[[2021,2,20]],"date-time":"2021-02-20T23:15:47Z","timestamp":1613862947000},"page":"81-92","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":79,"title":["AutoBridge"],"prefix":"10.1145","author":[{"given":"Licheng","family":"Guo","sequence":"first","affiliation":[{"name":"University of California, Los Angeles, Los Angeles, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuze","family":"Chi","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles, Los Angeles, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jie","family":"Wang","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles, Los Angeles, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jason","family":"Lau","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles, Los Angeles, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Weikang","family":"Qiao","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles, Los Angeles, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ecenur","family":"Ustun","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiru","family":"Zhang","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jason","family":"Cong","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles, Los Angeles, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2021,2,17]]},"reference":[{"key":"e_1_3_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554775"},{"key":"e_1_3_2_2_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689063"},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/3437539.3437574"},{"key":"e_1_3_2_2_4_1","doi-asserted-by":"crossref","unstructured":"Charles E Leiserson and James B Saxe. \"Retiming synchronous circuitry\". Algorithmica 6. 1--6 (1991) pp. 5--35.  Charles E Leiserson and James B Saxe. \"Retiming synchronous circuitry\". Algorithmica 6. 1--6 (1991) pp. 5--35.","DOI":"10.1007\/BF01759032"},{"key":"e_1_3_2_2_5_1","volume-title":"Xilinx UltraScale Plus Architecture","year":"2020","unstructured":"Xilinx. Xilinx UltraScale Plus Architecture . 2020 . url: https:\/\/www.xilinx.com\/products\/silicon-devices\/fpga\/virtex-ultrascale-plus.html. Xilinx. Xilinx UltraScale Plus Architecture. 2020. url: https:\/\/www.xilinx.com\/products\/silicon-devices\/fpga\/virtex-ultrascale-plus.html."},{"key":"e_1_3_2_2_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825872"},{"key":"e_1_3_2_2_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/268424.268425"},{"key":"e_1_3_2_2_8_1","unstructured":"Cadence. 2020. url: https:\/\/www.cadence.com\/.  Cadence. 2020. url: https:\/\/www.cadence.com\/."},{"key":"e_1_3_2_2_9_1","unstructured":"Synopsys. 2020. url: https:\/\/www.synopsys.com\/.  Synopsys. 2020. url: https:\/\/www.synopsys.com\/."},{"key":"e_1_3_2_2_10_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-95432-0_7"},{"key":"e_1_3_2_2_11_1","volume-title":"Xilinx Vitis Unified Platform","year":"2020","unstructured":"Xilinx. Xilinx Vitis Unified Platform . 2020 . url: https:\/\/www.xilinx.com\/products\/design-tools\/vitis\/vitis-platform.html. Xilinx. Xilinx Vitis Unified Platform. 2020. url: https:\/\/www.xilinx.com\/products\/design-tools\/vitis\/vitis-platform.html."},{"key":"e_1_3_2_2_12_1","volume-title":"Benchmarking and Bandwidth Optimization\". arXiv preprint arXiv:2010.06075","author":"Chi Yuze","year":"2020","unstructured":"Young-kyu Choi, Yuze Chi , Jie Wang , Licheng Guo , and Jason Cong . \" When HLS Meets FPGA HBM : Benchmarking and Bandwidth Optimization\". arXiv preprint arXiv:2010.06075 ( 2020 ). Young-kyu Choi, Yuze Chi, Jie Wang, Licheng Guo, and Jason Cong. \"When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization\". arXiv preprint arXiv:2010.06075 (2020)."},{"key":"e_1_3_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439301"},{"key":"e_1_3_2_2_14_1","unstructured":"Xilinx-HBM. 2020. url: https:\/\/www.xilinx.com\/products\/silicon-devices\/fpga\/virtex-ultrascale-plus-hbm.html.  Xilinx-HBM. 2020. url: https:\/\/www.xilinx.com\/products\/silicon-devices\/fpga\/virtex-ultrascale-plus-hbm.html."},{"key":"e_1_3_2_2_15_1","volume-title":"Intel Stratix 10 FPGA","year":"2020","unstructured":"Intel. Intel Stratix 10 FPGA . 2020 . url: https:\/\/www.intel.com\/content\/dam\/ www\/programmable\/us\/en\/pdfs\/literature\/hb\/stratix-10\/s10-overview.pdf. Intel. Intel Stratix 10 FPGA. 2020. url: https:\/\/www.intel.com\/content\/dam\/ www\/programmable\/us\/en\/pdfs\/literature\/hb\/stratix-10\/s10-overview.pdf."},{"key":"e_1_3_2_2_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/800262.809144"},{"key":"e_1_3_2_2_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1985.1270101"},{"key":"e_1_3_2_2_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775984"},{"key":"e_1_3_2_2_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/117009.117015"},{"key":"e_1_3_2_2_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1987.13876"},{"key":"e_1_3_2_2_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.945302"},{"key":"e_1_3_2_2_22_1","volume-title":"VLSI digital signal processing systems: design and implementation","author":"Parhi Keshab K","year":"2007","unstructured":"Keshab K Parhi . VLSI digital signal processing systems: design and implementation . John Wiley & Sons , 2007 . Keshab K Parhi. VLSI digital signal processing systems: design and implementation. John Wiley & Sons, 2007."},{"key":"e_1_3_2_2_23_1","unstructured":"Minimum-Cut. 2020. url: https:\/\/en.wikipedia.org\/wiki\/Minimum_cut.  Minimum-Cut. 2020. url: https:\/\/en.wikipedia.org\/wiki\/Minimum_cut."},{"key":"e_1_3_2_2_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147025"},{"key":"e_1_3_2_2_25_1","volume-title":"Vivado High-Level Synthesis","year":"2020","unstructured":"Xilinx. Vivado High-Level Synthesis . 2020 . url: https:\/\/www.xilinx.com\/products\/design-tools\/vivado\/integration\/esl-design.html. Xilinx. Vivado High-Level Synthesis. 2020. url: https:\/\/www.xilinx.com\/products\/design-tools\/vivado\/integration\/esl-design.html."},{"key":"e_1_3_2_2_26_1","unstructured":"H.G. Santos and T.A.M. Toffolo. Python MIP (Mixed-Integer Linear Programming) Tools. 2020. url: https:\/\/pypi.org\/project\/mip\/.  H.G. Santos and T.A.M. Toffolo. Python MIP (Mixed-Integer Linear Programming) Tools. 2020. url: https:\/\/pypi.org\/project\/mip\/."},{"key":"e_1_3_2_2_27_1","unstructured":"Gurobi. 2020. url: https:\/\/www.gurobi.com\/.  Gurobi. 2020. url: https:\/\/www.gurobi.com\/."},{"key":"e_1_3_2_2_28_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-16214-0_42"},{"key":"e_1_3_2_2_29_1","volume-title":"arXiv preprint arXiv:2009.11389","author":"Chi Yuze","year":"2020","unstructured":"Yuze Chi , Licheng Guo , Young-kyu Choi, Jie Wang , and Jason Cong . \" Extending High-Level Synthesis for Task-Parallel Programs\". arXiv preprint arXiv:2009.11389 ( 2020 ). Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, and Jason Cong. \"Extending High-Level Synthesis for Task-Parallel Programs\". arXiv preprint arXiv:2009.11389 (2020)."},{"key":"e_1_3_2_2_30_1","volume-title":"Vivado Design Suite","year":"2020","unstructured":"Xilinx. Vivado Design Suite . 2020 . url: https:\/\/www.xilinx.com\/products\/designtools\/vivado.html. Xilinx. Vivado Design Suite. 2020. url: https:\/\/www.xilinx.com\/products\/designtools\/vivado.html."},{"key":"e_1_3_2_2_31_1","unstructured":"url: https:\/\/doi.org\/10.5281\/zenodo.4412047.  url: https:\/\/doi.org\/10.5281\/zenodo.4412047."},{"key":"e_1_3_2_2_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICC.2018.8422855"},{"key":"e_1_3_2_2_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00027"},{"key":"e_1_3_2_2_34_1","doi-asserted-by":"publisher","DOI":"10.1093\/bioinformatics\/bty191"},{"key":"e_1_3_2_2_35_1","first-page":"1","volume-title":"2018 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). IEEE.","author":"Cong Jason","year":"2018","unstructured":"Jason Cong and Jie Wang . \"PolySA : polyhedral-based systolic array autocompilation \". 2018 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). IEEE. 2018 , pp. 1 -- 8 . Jason Cong and Jie Wang. \"PolySA: polyhedral-based systolic array autocompilation\". 2018 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). IEEE. 2018, pp. 1--8."},{"key":"e_1_3_2_2_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00033"},{"key":"e_1_3_2_2_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439292"},{"key":"e_1_3_2_2_38_1","unstructured":"Xilinx-Vitis-Library. 2020. url: https:\/\/github.com\/Xilinx\/Vitis_Libraries.  Xilinx-Vitis-Library. 2020. url: https:\/\/github.com\/Xilinx\/Vitis_Libraries."},{"key":"e_1_3_2_2_39_1","unstructured":"Intel-OpenCL-Examples. 2020. url: https:\/\/www.intel.com\/content\/www\/ us\/en\/programmable\/products\/design-software\/embedded-software-developers\/opencl\/support.html.  Intel-OpenCL-Examples. 2020. url: https:\/\/www.intel.com\/content\/www\/ us\/en\/programmable\/products\/design-software\/embedded-software-developers\/opencl\/support.html."},{"key":"e_1_3_2_2_40_1","first-page":"1130","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE.","author":"Zhao Jieru","year":"2019","unstructured":"Jieru Zhao , Tingyuan Liang , Sharad Sinha , and Wei Zhang . \"Machine learning based routing congestion prediction in FPGA high-level synthesis\". 2019 Design , Automation & Test in Europe Conference & Exhibition (DATE). IEEE. 2019 , pp. 1130 -- 1135 . Jieru Zhao, Tingyuan Liang, Sharad Sinha, and Wei Zhang. \"Machine learning based routing congestion prediction in FPGA high-level synthesis\". 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE. 2019, pp. 1130--1135."},{"key":"e_1_3_2_2_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00028"},{"key":"e_1_3_2_2_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT47387.2019.00071"},{"key":"e_1_3_2_2_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702071"},{"key":"e_1_3_2_2_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580064"},{"key":"e_1_3_2_2_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/GLSV.1994.290003"},{"key":"e_1_3_2_2_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/2902961.2903025"},{"key":"e_1_3_2_2_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554776"},{"key":"e_1_3_2_2_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2478280"},{"key":"e_1_3_2_2_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.748202"},{"key":"e_1_3_2_2_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00021"},{"key":"e_1_3_2_2_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378491"},{"key":"e_1_3_2_2_52_1","doi-asserted-by":"publisher","DOI":"10.5555\/1521436"},{"key":"e_1_3_2_2_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882481"},{"key":"e_1_3_2_2_54_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2015738"},{"key":"e_1_3_2_2_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2015.7393136"},{"key":"e_1_3_2_2_56_1","doi-asserted-by":"crossref","first-page":"182","DOI":"10.1145\/62882.62901","volume-title":"Papers on Twenty-five years of electronic design automation","author":"Lauther Ulrich","year":"1988","unstructured":"Ulrich Lauther . \" A min-cut placement algorithm for general cell assemblies based on a graph representation\". Papers on Twenty-five years of electronic design automation . 1988 , pp. 182 -- 191 . Ulrich Lauther. \"A min-cut placement algorithm for general cell assemblies based on a graph representation\". Papers on Twenty-five years of electronic design automation. 1988, pp. 182--191."},{"key":"e_1_3_2_2_57_1","first-page":"477","volume-title":"A global floorplanning approach for VLSI design","author":"La Potin David P","year":"1986","unstructured":"David P La Potin and Stephen W Director . \"Mason : A global floorplanning approach for VLSI design \". IEEE transactions on computer-aided design of integrated circuits and systems 5.4 ( 1986 ), pp. 477 -- 489 . David P La Potin and Stephen W Director. \"Mason: A global floorplanning approach for VLSI design\". IEEE transactions on computer-aided design of integrated circuits and systems 5.4 (1986), pp. 477--489."},{"issue":"13","key":"e_1_3_2_2_58_1","first-page":"38","article-title":"AN AUTOMATIC FLOORPLANNER FOR UP TO 100,000 GATES","volume":"8","author":"Modarres H","year":"1987","unstructured":"H Modarres and A Kelapure . \" AN AUTOMATIC FLOORPLANNER FOR UP TO 100,000 GATES \". VLSI Systems Design 8 . 13 ( 1987 ), p. 38 . H Modarres and A Kelapure. \"AN AUTOMATIC FLOORPLANNER FOR UP TO 100,000 GATES\". VLSI Systems Design 8.13 (1987), p. 38.","journal-title":"VLSI Systems Design"},{"key":"e_1_3_2_2_59_1","first-page":"471","article-title":"The semantics of a simple language for parallel programming","volume":"74","author":"Gilles KAHN","year":"1974","unstructured":"KAHN Gilles . \" The semantics of a simple language for parallel programming \". Information processing 74 ( 1974 ), pp. 471 -- 475 . KAHN Gilles. \"The semantics of a simple language for parallel programming\". Information processing 74 (1974), pp. 471--475.","journal-title":"Information processing"},{"key":"e_1_3_2_2_60_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2006.33"},{"key":"e_1_3_2_2_61_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337441"},{"key":"e_1_3_2_2_62_1","first-page":"227","volume-title":"International Conference on Computer Aided Design (IEEE Cat. No. 03CH37486)","author":"Lu Ruibing","year":"2003","unstructured":"Ruibing Lu and Cheng-Kok Koh . \"Performance optimization of latency insensitive systems through buffer queue sizing of communication channels\". ICCAD-2003 . International Conference on Computer Aided Design (IEEE Cat. No. 03CH37486) . IEEE. 2003 , pp. 227 -- 231 . Ruibing Lu and Cheng-Kok Koh. \"Performance optimization of latency insensitive systems through buffer queue sizing of communication channels\". ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No. 03CH37486). IEEE. 2003, pp. 227--231."},{"key":"e_1_3_2_2_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.854636"},{"key":"e_1_3_2_2_64_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278586"},{"key":"e_1_3_2_2_65_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00068"},{"key":"e_1_3_2_2_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.30"},{"key":"e_1_3_2_2_67_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375314"},{"key":"e_1_3_2_2_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174264"},{"key":"e_1_3_2_2_69_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375297"}],"event":{"name":"FPGA '21: The 2021 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","location":"Virtual Event USA","acronym":"FPGA '21","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["The 2021 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3431920.3439289","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3431920.3439289","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3431920.3439289","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:31:31Z","timestamp":1750195891000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3431920.3439289"}},"subtitle":["Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs"],"short-title":[],"issued":{"date-parts":[[2021,2,17]]},"references-count":69,"alternative-id":["10.1145\/3431920.3439289","10.1145\/3431920"],"URL":"https:\/\/doi.org\/10.1145\/3431920.3439289","relation":{},"subject":[],"published":{"date-parts":[[2021,2,17]]},"assertion":[{"value":"2021-02-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}