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The spike sorter constitutes a two-step trainer module that is shared by the signal acquisition channel associated with multiple electrodes. A low-power Spiking Neural Network (SNN) module is responsible for assigning the spike class. The two-step shared supervised on-chip training module is presented for improved training accuracy for the SNN. Post implant, the relatively power-hungry training module can be activated conditionally based on a statistics-driven retraining algorithm that allows on the fly training and adaptation. A low-power analog implementation for the SNN classifier is proposed based on resistive crossbar memory exploiting its approximate computing nature. Owing to the direct mapping of SNN functionality using physical characteristics of devices, the analog mode implementation can achieve \u223c21 \u00d7 lower power than its fully digital counterpart. We also incorporate the effect of device variation in the training process to suppress the impact of inevitable inaccuracies in such resistive crossbar devices on the classification accuracy. A variation-aware, digitally calibrated analog front-end is also presented, which consumes less than \u223c50 nW power and interfaces with the digital training module as well as the analog SNN spike sorting module. Hence, the proposed scheme is a low-power, variation-tolerant, adaptive, digitally trained, all-analog spike sorter device, applicable to implantable and wearable multichannel brain-machine interfaces.<\/jats:p>","DOI":"10.1145\/3432814","type":"journal-article","created":{"date-parts":[[2021,1,20]],"date-time":"2021-01-20T11:18:57Z","timestamp":1611141537000},"page":"1-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Power-efficient Spike Sorting Scheme Using Analog Spiking Neural Network Classifier"],"prefix":"10.1145","volume":"17","author":[{"given":"Anand Kumar","family":"Mukhopadhyay","sequence":"first","affiliation":[{"name":"Indian Institute of Technology Kharagpur, Kharagpur, India"}]},{"given":"Atul","family":"Sharma","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Kharagpur, Kharagpur, India"}]},{"given":"Indrajit","family":"Chakrabarti","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Kharagpur, Kharagpur, India"}]},{"given":"Arindam","family":"Basu","sequence":"additional","affiliation":[{"name":"Nanyang Technological University Singapore, Singapore"}]},{"given":"Mrigank","family":"Sharad","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Kharagpur, Kharagpur, India"}]}],"member":"320","published-online":{"date-parts":[[2021,1,20]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the IEEE Computer Society Annual Symposium on VLSI (IVLSI\u201917)","author":"Pathak R.","unstructured":"R. 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