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These innovations provide a platform that can leverage the improving technology of depth sensors and embedded accelerators to enable higher-resolution, lower-latency processing for 3D scenes using depth-upsampling algorithms. This research demonstrates that filter-based upsampling algorithms are feasible for mixed-reality apps using low-power hardware accelerators. The authors parallelized and evaluated a depth-upsampling algorithm on two different devices: a reconfigurable-logic FPGA embedded within a low-power SoC; and a fixed-logic embedded graphics processing unit. We demonstrate that both accelerators can meet the real-time requirements of 11 ms latency for mixed-reality apps.\n            <jats:sup>1<\/jats:sup>\n          <\/jats:p>","DOI":"10.1145\/3436878","type":"journal-article","created":{"date-parts":[[2021,3,27]],"date-time":"2021-03-27T16:05:47Z","timestamp":1616861147000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Real-time, High-resolution Depth Upsampling on Embedded Accelerators"],"prefix":"10.1145","volume":"20","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8777-4655","authenticated-orcid":false,"given":"David","family":"Langerman","sequence":"first","affiliation":[{"name":"NSF SHREC Center, ECE Dept., University of Pittsburgh, Pittsburgh, Pennsylvania"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alan","family":"George","sequence":"additional","affiliation":[{"name":"NSF SHREC Center, ECE Dept., University of Pittsburgh, Pittsburgh, Pennsylvania"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2021,3,27]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"NVIDIA. 2020. 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