{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,9]],"date-time":"2025-11-09T03:47:09Z","timestamp":1762660029684,"version":"3.41.0"},"reference-count":30,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2021,3,27]],"date-time":"2021-03-27T00:00:00Z","timestamp":1616803200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"This work was supported by Institute for Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea governmen","award":["2019-0-00033"],"award-info":[{"award-number":["2019-0-00033"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2021,5,31]]},"abstract":"<jats:p>We present an optimized implementation of the post-quantum Supersingular Isogeny Key Encapsulation (SIKE) for 32-bit ARMv7-A processors supporting NEON engine (i.e., SIMD instruction). Unlike previous SIKE implementations, finite field arithmetic is efficiently implemented in a redundant representation, which avoids carry propagation and pipeline stall. Furthermore, we adopted several state-of-the-art engineering techniques as well as hand-crafted assembly implementation for high performance. Optimized implementations are ported to Microsoft SIKE library written in \u201ca non-redundant representation\u201d and evaluated in high-end 32-bit ARMv7-A processors, such as ARM Cortex-A5, A7, and A15. A full key-exchange execution of SIKEp503 is performed in about 109 million cycles on ARM Cortex-A15 processors (i.e., 54.5 ms @2.0 GHz), which is about 1.58\u00d7 faster than previous state-of-the-art work presented in CHES\u201918.<\/jats:p>","DOI":"10.1145\/3439733","type":"journal-article","created":{"date-parts":[[2021,3,27]],"date-time":"2021-03-27T16:05:47Z","timestamp":1616861147000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["SIKE in 32-bit ARM Processors Based on Redundant Number System for NIST Level-II"],"prefix":"10.1145","volume":"20","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0069-9061","authenticated-orcid":false,"given":"Hwajeong","family":"Seo","sequence":"first","affiliation":[{"name":"College of IT Engineering at Hansung University, Seoul, Republic of Korea"}]},{"given":"Pakize","family":"Sanal","sequence":"additional","affiliation":[{"name":"Department of Computer, Electrical Engineering and Computer Science at Florida Atlantic University, Boca Raton, FL, USA"}]},{"given":"Reza","family":"Azarderakhsh","sequence":"additional","affiliation":[{"name":"Department of Computer, Electrical Engineering and Computer Science at Florida Atlantic University, Boca Raton, FL, USA"}]}],"member":"320","published-online":{"date-parts":[[2021,3,27]]},"reference":[{"volume-title":"Basil Hess, Amir Jalali, David Jao, Brian Koziel, Brian LaMacchia, Patrick Longa, Michael Naehrig, Geovandro Pereira, Joost Renes, Vladimir Soukharev, and David Urbanik.","year":"2019","author":"Azarderakhsh Reza","key":"e_1_2_1_1_1"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-03356-8_19"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-44709-3_18"},{"volume-title":"Bernstein and Peter Schwabe","year":"2012","author":"Daniel","key":"e_1_2_1_4_1"},{"volume-title":"Zaverucha","year":"2013","author":"Bos Joppe W.","key":"e_1_2_1_5_1"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-53018-4_21"},{"key":"e_1_2_1_7_1","unstructured":"Craig Costello Patrick Longa and Michael Naehrig. 2016--2018. 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Springer, 501--519","year":"2016","author":"Longa Patrick","key":"e_1_2_1_18_1"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PADW.2014.10"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694805.2694809"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1090\/S0025-5718-1985-0777282-X"},{"key":"e_1_2_1_22_1","unstructured":"NIST. 2017--2019. Post-Quantum Cryptography Standardization. Retrieved from https:\/\/csrc.nist.gov\/projects\/post-quantum-cryptography\/post-quantum-cryptography-standardization.  NIST. 2017--2019. Post-Quantum Cryptography Standardization. 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