{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T06:23:59Z","timestamp":1751091839352,"version":"3.41.0"},"reference-count":67,"publisher":"Association for Computing Machinery (ACM)","issue":"5","license":[{"start":{"date-parts":[[2021,6,5]],"date-time":"2021-06-05T00:00:00Z","timestamp":1622851200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2021,9,30]]},"abstract":"<jats:p>Side channel analysis attacks employ the emanated side channel information to deduce the secret keys from cryptographic implementations by analyzing the power traces during execution or scrutinizing faulty outputs. To be effective, a countermeasure must remove or conceal as many as possible side channels. However, many of the countermeasures against side channel attacks are applied independently.<\/jats:p>\n          <jats:p>\n            In this article, the authors present a novel countermeasure (referred to as\n            <jats:italic>QuadSeal<\/jats:italic>\n            ) against Power Analysis Attacks and Electromagentic Fault Injection Attacks (FIAs), which is an extension of the work proposed in Reference\u00a0[27]. The proposed solution relies on algorithmically balancing both Hamming distances and Hamming weights (where the bit transitions on the registers and gates are balanced, and the total number of 1s and 0s are balanced) by the use of four identical circuits with differing inputs and modified SubByte tables. By randomly rotating the four encryptions, the system is protected against variations, path imbalances, and aging effects. After generating the ciphertext, the output of each circuit is compared against each other to detect any fault injections or to correct the faulty ciphertext to gain reliability.\n          <\/jats:p>\n          <jats:p>The proposed countermeasure allows components to be switched off to save power or to run four executions in parallel for high performance when resistance against power analysis attacks is not of high priority, which is not available with the existing countermeasures (except software based where source code can be changed). The proposed countermeasure is implemented for Advanced Encryption Standard (AES) and tested against Correlation Power Analysis and Mutual Information Attacks attacks (for up to a million traces), and none of the secret keys was found even after one million power traces (the unprotected AES circuit is vulnerable for power analysis attacks within 5,000 power traces). A detection circuit (referred to as C-FIA circuit) is operated using the algorithmic redundancy presented in four circuits of QuadSeal to mitigate Electromagnetic Fault Injection Attacks. Using Synopsys PrimeTime, we measured the power dissipation of QuadSeal registers and XOR gates to test the effectiveness of Quadruple balancing methodology. We tested the QuadSeal countermeasure with C-FIA circuit against Differential Fault Analysis Attacks up to one million traces; no bytes of the secret key were found. This is the smallest known circuit that is capable of withstanding power-based side channel attacks when electromagnetic injection attack resistance, process variations, path imbalances, and aging effects are considered.<\/jats:p>","DOI":"10.1145\/3443706","type":"journal-article","created":{"date-parts":[[2021,6,5]],"date-time":"2021-06-05T23:29:13Z","timestamp":1622935753000},"page":"1-36","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks"],"prefix":"10.1145","volume":"26","author":[{"given":"Darshana","family":"Jayasinghe","sequence":"first","affiliation":[{"name":"University of New South Wales, NSW, Australia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aleksandar","family":"Ignjatovic","sequence":"additional","affiliation":[{"name":"University of New South Wales, NSW, Australia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roshan","family":"Ragel","sequence":"additional","affiliation":[{"name":"University of Peradeniya, Sri lanka"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jude Angelo","family":"Ambrose","sequence":"additional","affiliation":[{"name":"Seeing Machines, Fyshwick, Australia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sri","family":"Parameswaran","sequence":"additional","affiliation":[{"name":"University of New South Wales, NSW, Australia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2021,6,5]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"[n.d.]. Federal Information Processing Standards Publication 197 Announcing the Advanced Encryption Standard (AES). Retrieved from http:\/\/csrc.nist.gov\/publications\/fips\/fips197\/fips-197.pdf.  [n.d.]. Federal Information Processing Standards Publication 197 Announcing the Advanced Encryption Standard (AES). Retrieved from http:\/\/csrc.nist.gov\/publications\/fips\/fips197\/fips-197.pdf."},{"volume-title":"PrimeTime Basics","key":"e_1_2_1_2_1","unstructured":"2002. PrimeTime Basics . Springer US , Boston, MA , 239\u2013259. DOI:https:\/\/doi.org\/10.1007\/0-306-47507-3_12 10.1007\/0-306-47507-3_12 2002. PrimeTime Basics. Springer US, Boston, MA, 239\u2013259. DOI:https:\/\/doi.org\/10.1007\/0-306-47507-3_12"},{"key":"e_1_2_1_3_1","unstructured":"2017. TSMC 65nm Technology. Retrieved from https:\/\/www.tsmc.com\/english\/dedicatedFoundry\/technology\/65nm.htm.  2017. TSMC 65nm Technology. Retrieved from https:\/\/www.tsmc.com\/english\/dedicatedFoundry\/technology\/65nm.htm."},{"key":"e_1_2_1_4_1","unstructured":"2020. Synopsys PrimeTime. Retrieved from https:\/\/www.synopsys.com\/support\/training\/signoff\/primetime1-fcd.html.  2020. Synopsys PrimeTime. Retrieved from https:\/\/www.synopsys.com\/support\/training\/signoff\/primetime1-fcd.html."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2009.0097"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/1509456.1509605"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/1509456.1509605"},{"volume-title":"Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI13)","author":"Arora Ankita","key":"e_1_2_1_8_1","unstructured":"Ankita Arora , Jude Angelo Ambrose , Jorgen Peddersen , and Sri Parameswaran . [n.d.]. A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES . In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI13) . 76\u201383. Ankita Arora, Jude Angelo Ambrose, Jorgen Peddersen, and Sri Parameswaran. [n.d.]. A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI13). 76\u201383."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-008-9017-z"},{"volume-title":"Proceedings of the 2011 6th International Conference on Computer Sciences and Convergence Information Technology (ICCIT\u201911)","author":"Bae K.","key":"e_1_2_1_10_1","unstructured":"K. Bae , S. Moon , D. Choi , Y. Choi , D. s. Choi , and J. Ha . 2011. Differential fault analysis on AES by round reduction . In Proceedings of the 2011 6th International Conference on Computer Sciences and Convergence Information Technology (ICCIT\u201911) . 607\u2013612. K. Bae, S. Moon, D. Choi, Y. Choi, D. s. Choi, and J. Ha. 2011. Differential fault analysis on AES by round reduction. In Proceedings of the 2011 6th International Conference on Computer Sciences and Convergence Information Technology (ICCIT\u201911). 607\u2013612."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/646762.706179"},{"volume-title":"Proceedings of the International Conference Mixed Design of Integrated Circuits and Systems (MIXDES\u201913)","author":"Bongiovanni S.","key":"e_1_2_1_12_1","unstructured":"S. Bongiovanni , M. Olivieri , G. Scotti , and A. Trifiletti . [n.d.]. A flip-flop implementation for the DPA-resistant delay-based dual-rail pre-charge logic family . In Proceedings of the International Conference Mixed Design of Integrated Circuits and Systems (MIXDES\u201913) . 163\u2013168. S. Bongiovanni, M. Olivieri, G. Scotti, and A. Trifiletti. [n.d.]. A flip-flop implementation for the DPA-resistant delay-based dual-rail pre-charge logic family. In Proceedings of the International Conference Mixed Design of Integrated Circuits and Systems (MIXDES\u201913). 163\u2013168."},{"volume-title":"Proceedings of the Annual Conference on Cryptographic Hardware and Embedded Systems (CHES\u201904)","author":"Brier Eric","key":"e_1_2_1_13_1","unstructured":"Eric Brier , Christophe Clavier , and Francis Olivier . [n.d.]. Correlation power analysis with a leakage model . In Proceedings of the Annual Conference on Cryptographic Hardware and Embedded Systems (CHES\u201904) . 16\u201329. Eric Brier, Christophe Clavier, and Francis Olivier. [n.d.]. Correlation power analysis with a leakage model. In Proceedings of the Annual Conference on Cryptographic Hardware and Embedded Systems (CHES\u201904). 16\u201329."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-45608-8_19"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1007\/11894063_20"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2996366.2996428"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2012.15"},{"volume-title":"SafeDRP: Yet another way toward power-equalized designs in FPGA","author":"Ender Maik","key":"e_1_2_1_18_1","unstructured":"Maik Ender , Alexander Wild , and Amir Moradi . 2017. SafeDRP: Yet another way toward power-equalized designs in FPGA . In Constructive Side-Channel Analysis and Secure Design, Sylvain Guilley (Ed.). Springer International Publishing , Cham , 83\u2013101. Maik Ender, Alexander Wild, and Amir Moradi. 2017. SafeDRP: Yet another way toward power-equalized designs in FPGA. In Constructive Side-Channel Analysis and Secure Design, Sylvain Guilley (Ed.). Springer International Publishing, Cham, 83\u2013101."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-25283-9_17"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-85053-3_27"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-33481-8_17"},{"key":"e_1_2_1_22_1","doi-asserted-by":"crossref","unstructured":"Sylvain Guilley Sumanta Chaudhuri Laurent Sauvage Tarik Graba Jean-Luc Danger Philippe Hoogvorst Vinh-Nga Vong Maxime Nassar and Florent Flament. 2009. Shall we trust WDDL? In Future of Trust in Computing. 208\u2013215.  Sylvain Guilley Sumanta Chaudhuri Laurent Sauvage Tarik Graba Jean-Luc Danger Philippe Hoogvorst Vinh-Nga Vong Maxime Nassar and Florent Flament. 2009. Shall we trust WDDL? In Future of Trust in Computing. 208\u2013215.","DOI":"10.1007\/978-3-8348-9324-6_22"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228463"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1057661.1057677"},{"volume-title":"Proceedings of the Global Conference on Consumer Electronics (GCCE\u201912)","author":"Hori Y.","key":"e_1_2_1_25_1","unstructured":"Y. Hori , T. Katashita , A. Sasaki , and A. Satoh . 2012. SASEBO-GIII: A hardware security evaluation board equipped with a 28-nm FPGA . In Proceedings of the Global Conference on Consumer Electronics (GCCE\u201912) . 657\u2013660. Y. Hori, T. Katashita, A. Sasaki, and A. Satoh. 2012. SASEBO-GIII: A hardware security evaluation board equipped with a 28-nm FPGA. In Proceedings of the Global Conference on Consumer Electronics (GCCE\u201912). 657\u2013660."},{"key":"e_1_2_1_26_1","volume-title":"Proceedings of the IEEE 1st Global Conference on Consumer Electronics (GCCE\u201912)","author":"Hori Y.","year":"2012","unstructured":"Y. Hori , T. Katashita , A. Sasaki , and A. Satoh . 2012. SASEBO-GIII: A hardware security evaluation board equipped with a 28-nm FPGA . In Proceedings of the IEEE 1st Global Conference on Consumer Electronics (GCCE\u201912) . 657\u2013660. DOI:https:\/\/doi.org\/10.1109\/GCCE. 2012 .6379944 10.1109\/GCCE.2012.6379944 Y. Hori, T. Katashita, A. Sasaki, and A. Satoh. 2012. SASEBO-GIII: A hardware security evaluation board equipped with a 28-nm FPGA. In Proceedings of the IEEE 1st Global Conference on Consumer Electronics (GCCE\u201912). 657\u2013660. DOI:https:\/\/doi.org\/10.1109\/GCCE.2012.6379944"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.5555\/2830689.2830692"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2017.25"},{"key":"e_1_2_1_29_1","volume-title":"Proceedings of the International Conference on Computer Design (ICCD\u201914)","author":"Jayasinghe D.","year":"2014","unstructured":"D. Jayasinghe , R. Ragel , J.A. Ambrose , A. Ignjatovic , and S. Parameswaran . 2014. Advanced modes in AES: Are they safe from power analysis based side channel attacks? In Proceedings of the International Conference on Computer Design (ICCD\u201914) . 173\u2013180. DOI:https:\/\/doi.org\/10.1109\/ICCD. 2014 .6974678 10.1109\/ICCD.2014.6974678 D. Jayasinghe, R. Ragel, J.A. Ambrose, A. Ignjatovic, and S. Parameswaran. 2014. Advanced modes in AES: Are they safe from power analysis based side channel attacks? In Proceedings of the International Conference on Computer Design (ICCD\u201914). 173\u2013180. DOI:https:\/\/doi.org\/10.1109\/ICCD.2014.6974678"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-ifs:20060163"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.5555\/647834.738167"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804378"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2004.834620"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACSAC.2009.14"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-011-0006-y"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.5555\/646764.703989"},{"volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS\u201908)","author":"Li Liang","key":"e_1_2_1_37_1","unstructured":"Liang Li , Jun Han , Xiaoyang Zeng , and Jia Zhao . [n.d.]. A full-custom design of AES SubByte module with signal independent power consumption . In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS\u201908) . 3302\u20133305. Liang Li, Jun Han, Xiaoyang Zeng, and Jia Zhao. [n.d.]. A full-custom design of AES SubByte module with signal independent power consumption. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS\u201908). 3302\u20133305."},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2012.19"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.149"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1007\/11889700_15"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.5555\/1208234"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_12"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/1502781.1502784"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2017.04.014"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2160375"},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2160375"},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1007\/11894063_8"},{"key":"e_1_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.33"},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.5555\/1870926.1871133"},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2015.9"},{"volume-title":"Counteracting Power Analysis Attacks by Masking","author":"Oswald Elisabeth","key":"e_1_2_1_51_1","unstructured":"Elisabeth Oswald and Stefan Mangard . 2010. Counteracting Power Analysis Attacks by Masking . Springer US , Boston, MA , 159\u2013178. DOI:https:\/\/doi.org\/10.1007\/978-0-387-71829-3_9 10.1007\/978-0-387-71829-3_9 Elisabeth Oswald and Stefan Mangard. 2010. Counteracting Power Analysis Attacks by Masking. Springer US, Boston, MA, 159\u2013178. DOI:https:\/\/doi.org\/10.1007\/978-0-387-71829-3_9"},{"key":"e_1_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-21476-4_13"},{"key":"e_1_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74735-2_6"},{"key":"e_1_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_13"},{"key":"e_1_2_1_55_1","volume-title":"Proceedings of Austrian Workshop on Microelectronics (Austrochip\u201904)","author":"Pramstaller Norbert","year":"2004","unstructured":"Norbert Pramstaller , Maria Elisabeth Oswald , Stefan Mangard , Frank K. G\u00fcrkaynak , and Simon H\u00e4ne . 2004 . A masked AES ASIC implementation . In Proceedings of Austrian Workshop on Microelectronics (Austrochip\u201904) . 77\u201381. Norbert Pramstaller, Maria Elisabeth Oswald, Stefan Mangard, Frank K. G\u00fcrkaynak, and Simon H\u00e4ne. 2004. A masked AES ASIC implementation. In Proceedings of Austrian Workshop on Microelectronics (Austrochip\u201904). 77\u201381."},{"key":"e_1_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/1015047.1015049"},{"volume-title":"Fault Analysis in Cryptography","author":"Regazzoni Francesco","key":"e_1_2_1_57_1","unstructured":"Francesco Regazzoni , Luca Breveglieri , Paolo Ienne , and Israel Koren . 2012. Interaction between fault attack countermeasures and the resistance against power analysis attacks . In Fault Analysis in Cryptography . Springer , Berlin , 257\u2013272. Francesco Regazzoni, Luca Breveglieri, Paolo Ienne, and Israel Koren. 2012. Interaction between fault attack countermeasures and the resistance against power analysis attacks. In Fault Analysis in Cryptography. Springer, Berlin, 257\u2013272."},{"key":"e_1_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967005"},{"key":"e_1_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/584091.584093"},{"key":"e_1_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.61"},{"key":"e_1_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1007\/11894063_21"},{"key":"e_1_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855939"},{"key":"e_1_2_1_64_1","volume-title":"Proceedings of the 2019 4th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM\u201919)","author":"Tziouvaras A.","year":"2019","unstructured":"A. Tziouvaras , G. Dimitriou , M. Dossis , and G. Stamoulis . 2019. Instruction-based timing analysis in pipelined processors . In Proceedings of the 2019 4th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM\u201919) . 1\u20136. DOI:https:\/\/doi.org\/10.1109\/SEEDA-CECNSM. 2019 .8908287 10.1109\/SEEDA-CECNSM.2019.8908287 A. Tziouvaras, G. Dimitriou, M. Dossis, and G. Stamoulis. 2019. Instruction-based timing analysis in pipelined processors. In Proceedings of the 2019 4th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM\u201919). 1\u20136. DOI:https:\/\/doi.org\/10.1109\/SEEDA-CECNSM.2019.8908287"},{"key":"e_1_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.5555\/1116164.1116582"},{"key":"e_1_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289831"},{"key":"e_1_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1145\/3212480.3226104"},{"key":"e_1_2_1_68_1","first-page":"4","article-title":"Employing symmetric dual-rail logic to thwart LPA attack","volume":"5","author":"Zhu Nian-Hao","year":"2013","unstructured":"Nian-Hao Zhu , Yu-Jie Zhou , and Hong-Ming Liu . 2013 . Employing symmetric dual-rail logic to thwart LPA attack . IEEE Embed. Syst. Lett. 5 , 4 (Dec. 2013), 61\u201364. DOI:https:\/\/doi.org\/10.1109\/LES.2013.2279918 10.1109\/LES.2013.2279918 Nian-Hao Zhu, Yu-Jie Zhou, and Hong-Ming Liu. 2013. Employing symmetric dual-rail logic to thwart LPA attack. IEEE Embed. Syst. Lett. 5, 4 (Dec. 2013), 61\u201364. DOI:https:\/\/doi.org\/10.1109\/LES.2013.2279918","journal-title":"IEEE Embed. Syst. Lett."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3443706","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3443706","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:02:19Z","timestamp":1750197739000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3443706"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6,5]]},"references-count":67,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2021,9,30]]}},"alternative-id":["10.1145\/3443706"],"URL":"https:\/\/doi.org\/10.1145\/3443706","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2021,6,5]]},"assertion":[{"value":"2020-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-06-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}