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Syst."],"published-print":{"date-parts":[[2021,4,30]]},"abstract":"<jats:p>Singe-Electron Transistor (SET) is considered as a promising candidate of low-power devices for replacement or co-existence with Complementary Metal-Oxide-Semiconductor (CMOS) transistors\/circuits. In this work, we propose a diagnosis approach for SET array under a more generalized defect model. With the more generalized defect model, the diagnosis approach will become more practical but complicated. We conducted experiments on a set of SET arrays with different dimensions and defect rates. The experimental results show that our approach only has 3.8% false-negative rate and 0.7% misjudged-category rate on average without reporting any false-positive edge when the defect rate is 4%. Therefore, the proposed diagnosis approach can diagnose the defective SET arrays and elevate the reliability of the SET arrays in the synthesis flow.<\/jats:p>","DOI":"10.1145\/3444751","type":"journal-article","created":{"date-parts":[[2021,1,21]],"date-time":"2021-01-21T17:15:21Z","timestamp":1611249321000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model"],"prefix":"10.1145","volume":"17","author":[{"given":"Chia-Cheng","family":"Wu","sequence":"first","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan"}]},{"given":"Yi-Hsiang","family":"Hu","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu, Taiwan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0136-9825","authenticated-orcid":false,"given":"Chia-Chun","family":"Lin","sequence":"additional","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan"}]},{"given":"Yung-Chih","family":"Chen","sequence":"additional","affiliation":[{"name":"Yuan Ze University"}]},{"given":"Juinn-Dar","family":"Huang","sequence":"additional","affiliation":[{"name":"National Chiao Tung University"}]},{"given":"Chun-Yao","family":"Wang","sequence":"additional","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan"}]}],"member":"320","published-online":{"date-parts":[[2021,1,21]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/16.595938"},{"volume-title":"Proceedings of the Design Automation Conference. 878--883","author":"Chen Y.-C.","key":"e_1_2_1_2_1","unstructured":"Y.-C. Chen , S. Eachempati , C.-Y. Wang , S. Datta , Y. Xie , and V. Narayanan . 2011. Automated mapping for reconfigurable single-electron transistor arrays . In Proceedings of the Design Automation Conference. 878--883 . Y.-C. Chen, S. Eachempati, C.-Y. Wang, S. Datta, Y. Xie, and V. Narayanan. 2011. Automated mapping for reconfigurable single-electron transistor arrays. In Proceedings of the Design Automation Conference. 878--883."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463585.2463592"},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the Design Automation and Test in Europe. 1--4.","author":"Chen Y.-H.","year":"2014","unstructured":"Y.-H. Chen , J.-Y. Chen , and J.-D. Huang . 2014 . Area minimization synthesis for reconfigurable single-electron ttransistor arrays with fabrication constraints . In Proceedings of the Design Automation and Test in Europe. 1--4. Y.-H. Chen, J.-Y. Chen, and J.-D. Huang. 2014. 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