{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T13:23:29Z","timestamp":1773840209825,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":40,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,4,17]],"date-time":"2021-04-17T00:00:00Z","timestamp":1618617600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Intel","award":["ISRA Center, Gift"],"award-info":[{"award-number":["ISRA Center, Gift"]}]},{"name":"Georgia Tech IISP","award":["Cybersecurity Fellowship"],"award-info":[{"award-number":["Cybersecurity Fellowship"]}]},{"name":"NSF","award":["1954521, 1942888"],"award-info":[{"award-number":["1954521, 1942888"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,4,19]]},"DOI":"10.1145\/3445814.3446742","type":"proceedings-article","created":{"date-parts":[[2021,4,11]],"date-time":"2021-04-11T17:06:26Z","timestamp":1618160786000},"page":"1077-1090","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":32,"title":["Streamline: a fast, flushless cache covert-channel attack by enabling asynchronous collusion"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3542-2548","authenticated-orcid":false,"given":"Gururaj","family":"Saileshwar","sequence":"first","affiliation":[{"name":"Georgia Institute of Technology, USA"}]},{"given":"Christopher W.","family":"Fletcher","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1314-9096","authenticated-orcid":false,"given":"Moinuddin","family":"Qureshi","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, USA"}]}],"member":"320","published-online":{"date-parts":[[2021,4,17]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Manaar Alam Sarani Bhattacharya Debdeep Mukhopadhyay and Sourangshu Bhattacharya. 2017. Performance Counters to Rescue: A Machine Learning based safeguard against Micro-architectural Side-Channel-Attacks. IACR Cryptology ePrint Archive 2017 ( 2017 ) 564.  Manaar Alam Sarani Bhattacharya Debdeep Mukhopadhyay and Sourangshu Bhattacharya. 2017. Performance Counters to Rescue: A Machine Learning based safeguard against Micro-architectural Side-Channel-Attacks. IACR Cryptology ePrint Archive 2017 ( 2017 ) 564."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00066"},{"key":"e_1_3_2_1_3_1","volume-title":"Proceedings of the Linux Symposium.","author":"Arcangeli Andrea","year":"2009","unstructured":"Andrea Arcangeli , Izik Eidus , and Chris Wright . 2009 . Increasing memory density by using KSM . In Proceedings of the Linux Symposium. Andrea Arcangeli, Izik Eidus, and Chris Wright. 2009. Increasing memory density by using KSM. In Proceedings of the Linux Symposium."},{"key":"e_1_3_2_1_4_1","volume-title":"29th USENIX Security Symposium (USENIX Security 2020 ).","author":"Briongos Samira","year":"2020","unstructured":"Samira Briongos , Pedro Malag\u00f3n , Jos\u00e9 M Moya , and Thomas Eisenbarth . 2020 . RELOAD+ REFRESH: Abusing cache replacement policies to perform stealthy cache attacks . In 29th USENIX Security Symposium (USENIX Security 2020 ). Samira Briongos, Pedro Malag\u00f3n, Jos\u00e9 M Moya, and Thomas Eisenbarth. 2020. RELOAD+ REFRESH: Abusing cache replacement policies to perform stealthy cache attacks. In 29th USENIX Security Symposium (USENIX Security 2020 )."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.42"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"crossref","unstructured":"Marco Chiappetta Erkay Savas and Cemal Yilmaz. 2016. Real time detection of cache-based side-channel attacks using hardware performance counters. Applied Soft Computing 49 ( 2016 ) 1162-1174.  Marco Chiappetta Erkay Savas and Cemal Yilmaz. 2016. Real time detection of cache-based side-channel attacks using hardware performance counters. Applied Soft Computing 49 ( 2016 ) 1162-1174.","DOI":"10.1016\/j.asoc.2016.09.014"},{"key":"e_1_3_2_1_7_1","unstructured":"CPU-Monkey. (accessed January 15 2021 ). Comparing Intel Xeon E3-1270 v5 vs Intel Core i7-4790. https:\/\/www.cpu-monkey.com\/en\/compare_cpu-intel_xeon_e3_1270_v5-601-vs-intel_core_i7_4790-355.  CPU-Monkey. (accessed January 15 2021 ). Comparing Intel Xeon E3-1270 v5 vs Intel Core i7-4790. https:\/\/www.cpu-monkey.com\/en\/compare_cpu-intel_xeon_e3_1270_v5-601-vs-intel_core_i7_4790-355."},{"key":"e_1_3_2_1_8_1","volume-title":"ECE, and Dmitry Ponomarev.","author":"Evtyushkin Dmitry","year":"2018","unstructured":"Dmitry Evtyushkin , Ryan Riley , Nael CSE Abu-Ghazaleh , ECE, and Dmitry Ponomarev. 2018 . Branchscope : A new side-channel attack on directional branch predictor. ACM SIGPLAN Notices 53, 2 ( 2018 ), 693-707. Dmitry Evtyushkin, Ryan Riley, Nael CSE Abu-Ghazaleh, ECE, and Dmitry Ponomarev. 2018. Branchscope: A new side-channel attack on directional branch predictor. ACM SIGPLAN Notices 53, 2 ( 2018 ), 693-707."},{"key":"e_1_3_2_1_9_1","volume-title":"Shijia Wei, and Yasser Shalabi.","author":"Fletcher Christopher","year":"2019","unstructured":"Christopher Fletcher , Mohit Tiwari , Mengjia Yan , Mohamad El Hajj , Shijia Wei, and Yasser Shalabi. 2019 . Covert Channel Attack Tutorial at ISCA 2019. https: \/\/github.com\/yshalabi\/covert-channel-tutorial. Christopher Fletcher, Mohit Tiwari, Mengjia Yan, Mohamad El Hajj, Shijia Wei, and Yasser Shalabi. 2019. Covert Channel Attack Tutorial at ISCA 2019. https: \/\/github.com\/yshalabi\/covert-channel-tutorial."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2757667.2757672"},{"key":"e_1_3_2_1_11_1","first-page":"955","volume-title":"27th USENIX Security Symposium (USENIX Security 18)","author":"Gras Ben","year":"2018","unstructured":"Ben Gras , Kaveh Razavi , Herbert Bos , and Cristiano Giufrida . 2018 . Translation leak-aside bufer: Defeating cache side-channel protections with TLB attacks . In 27th USENIX Security Symposium (USENIX Security 18) . 955 - 972 . Ben Gras, Kaveh Razavi, Herbert Bos, and Cristiano Giufrida. 2018. Translation leak-aside bufer: Defeating cache side-channel protections with TLB attacks. In 27th USENIX Security Symposium (USENIX Security 18). 955-972."},{"key":"e_1_3_2_1_12_1","first-page":"1075","volume-title":"AutoLock: Why Cache Attacks on ARM Are Harder Than You Think. In 26th USENIX Security Symposium (USENIX Security 17)","author":"Green Marc","year":"2017","unstructured":"Marc Green , Leandro Rodrigues-Lima , Andreas Zankl , Gorka Irazoqui , Johann Heyszl , and Thomas Eisenbarth . 2017 . AutoLock: Why Cache Attacks on ARM Are Harder Than You Think. In 26th USENIX Security Symposium (USENIX Security 17) . 1075 - 1091 . Marc Green, Leandro Rodrigues-Lima, Andreas Zankl, Gorka Irazoqui, Johann Heyszl, and Thomas Eisenbarth. 2017. AutoLock: Why Cache Attacks on ARM Are Harder Than You Think. In 26th USENIX Security Symposium (USENIX Security 17). 1075-1091."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-40667-1_14"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815971"},{"key":"e_1_3_2_1_15_1","first-page":"189","volume-title":"STEALTHMEM: System-Level Protection Against Cache-Based Side Channel Attacks in the Cloud. In 21st USENIX Security Symposium (USENIX Security 12)","author":"Kim Taesoo","year":"2012","unstructured":"Taesoo Kim , Marcus Peinado , and Gloria Mainar-Ruiz . 2012 . STEALTHMEM: System-Level Protection Against Cache-Based Side Channel Attacks in the Cloud. In 21st USENIX Security Symposium (USENIX Security 12) . 189 - 204 . Taesoo Kim, Marcus Peinado, and Gloria Mainar-Ruiz. 2012. STEALTHMEM: System-Level Protection Against Cache-Based Side Channel Attacks in the Cloud. In 21st USENIX Security Symposium (USENIX Security 12). 189-204."},{"key":"e_1_3_2_1_16_1","unstructured":"Colin King. (accessed January 15 2021 ). Ubuntu Wiki: Stress-NG. https:\/\/wiki. ubuntu.com\/Kernel\/Reference\/stress-ng.  Colin King. (accessed January 15 2021 ). Ubuntu Wiki: Stress-NG. https:\/\/wiki. ubuntu.com\/Kernel\/Reference\/stress-ng."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00083"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00002"},{"key":"e_1_3_2_1_19_1","first-page":"549","volume-title":"25th USENIX Security Symposium (USENIX Security 16)","author":"Lipp Moritz","year":"2016","unstructured":"Moritz Lipp , Daniel Gruss , Raphael Spreitzer , Cl\u00e9mentine Maurice , and Stefan Mangard . 2016 . Armageddon: Cache attacks on mobile devices . In 25th USENIX Security Symposium (USENIX Security 16) . 549 - 564 . Moritz Lipp, Daniel Gruss, Raphael Spreitzer, Cl\u00e9mentine Maurice, and Stefan Mangard. 2016. Armageddon: Cache attacks on mobile devices. In 25th USENIX Security Symposium (USENIX Security 16). 549-564."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3320269.3384746"},{"key":"e_1_3_2_1_21_1","first-page":"973","volume-title":"27th USENIX Security Symposium (USENIX Security 18)","author":"Lipp Moritz","year":"2018","unstructured":"Moritz Lipp , Michael Schwarz , Daniel Gruss , Thomas Prescher , Werner Haas , Anders Fogh , Jann Horn , Stefan Mangard , Paul Kocher , Daniel Genkin , Yuval Yarom , and Mike Hamburg . 2018 . Meltdown: Reading kernel memory from user space . In 27th USENIX Security Symposium (USENIX Security 18) . 973 - 990 . Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Anders Fogh, Jann Horn, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, and Mike Hamburg. 2018. Meltdown: Reading kernel memory from user space. In 27th USENIX Security Symposium (USENIX Security 18). 973-990."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.28"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2015.43"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-20550-2_3"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-30806-7_9"},{"key":"e_1_3_2_1_26_1","volume-title":"Proceedings of BSDCan.","author":"Percival Colin","year":"2005","unstructured":"Colin Percival . 2005 . Cache missing for fun and profit . In Proceedings of BSDCan. Colin Percival. 2005. Cache missing for fun and profit. In Proceedings of BSDCan."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1655008.1655019"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080220"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-29959-0_14"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-60876-1_1"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3243734.3243736"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00081"},{"key":"e_1_3_2_1_33_1","unstructured":"Krishnaswamy Viswanathan. (accessed August 1 2020 ). Disclosure of Hardware Prefetcher Control on Some Intel Processors. https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/articles\/disclosure-ofhw-prefetcher-control-on-some-intel-processors.html.  Krishnaswamy Viswanathan. (accessed August 1 2020 ). Disclosure of Hardware Prefetcher Control on Some Intel Processors. https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/articles\/disclosure-ofhw-prefetcher-control-on-some-intel-processors.html."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"crossref","unstructured":"Jack Wampler Ian Martiny and Eric Wustrow. 2019. ExSpectre: Hiding Malware in Speculative Execution.. In NDSS.  Jack Wampler Ian Martiny and Eric Wustrow. 2019. ExSpectre: Hiding Malware in Speculative Execution.. In NDSS.","DOI":"10.14722\/ndss.2019.23409"},{"key":"e_1_3_2_1_35_1","first-page":"675","volume-title":"28th USENIX Security Symposium (USENIX Security 19)","author":"Werner Mario","year":"2019","unstructured":"Mario Werner , Thomas Unterluggauer , Lukas Giner , Michael Schwarz , Daniel Gruss , and Stefan Mangard . 2019 . ScatterCache: thwarting cache attacks via cache set randomization . In 28th USENIX Security Symposium (USENIX Security 19) . 675 - 692 . Mario Werner, Thomas Unterluggauer, Lukas Giner, Michael Schwarz, Daniel Gruss, and Stefan Mangard. 2019. ScatterCache: thwarting cache attacks via cache set randomization. In 28th USENIX Security Symposium (USENIX Security 19). 675-692."},{"key":"e_1_3_2_1_36_1","volume-title":"Leaking Information Through Cache LRU States. In 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 139-152","author":"Xiong Wenjie","year":"2020","unstructured":"Wenjie Xiong and Jakub Szefer . 2020 . Leaking Information Through Cache LRU States. In 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 139-152 . Wenjie Xiong and Jakub Szefer. 2020. Leaking Information Through Cache LRU States. In 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 139-152."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080222"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783742"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00024"},{"key":"e_1_3_2_1_40_1","first-page":"719","volume-title":"23rd USENIX Security Symposium (USENIX Security 14)","author":"Yarom Yuval","year":"2014","unstructured":"Yuval Yarom and Katrina Falkner . 2014 . FLUSH+ RELOAD: a high resolution, low noise, L3 cache side-channel attack . In 23rd USENIX Security Symposium (USENIX Security 14) . 719 - 732 . Yuval Yarom and Katrina Falkner. 2014. FLUSH+ RELOAD: a high resolution, low noise, L3 cache side-channel attack. In 23rd USENIX Security Symposium (USENIX Security 14). 719-732."}],"event":{"name":"ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems","location":"Virtual USA","acronym":"ASPLOS '21","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages"]},"container-title":["Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3445814.3446742","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3445814.3446742","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3445814.3446742","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:28:14Z","timestamp":1750195694000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3445814.3446742"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4,17]]},"references-count":40,"alternative-id":["10.1145\/3445814.3446742","10.1145\/3445814"],"URL":"https:\/\/doi.org\/10.1145\/3445814.3446742","relation":{},"subject":[],"published":{"date-parts":[[2021,4,17]]},"assertion":[{"value":"2021-04-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}