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Two technologies of interest are\n            <jats:italic>Posit<\/jats:italic>\n            and RISC-V.\n            <jats:italic>Posit<\/jats:italic>\n            was introduced in mid-2017 as a viable alternative to IEEE-754, and RISC-V provides a commercial-grade open source Instruction Set Architecture (ISA). In this article, we bring these two technologies together and propose a Configurable\n            <jats:italic>Posit<\/jats:italic>\n            Enabled RISC-V Core called PERI.\n          <\/jats:p>\n          <jats:p>\n            The article provides insights on how the Single-Precision Floating Point (\u201cF\u201d) extension of RISC-V can be leveraged to support\n            <jats:italic>posit<\/jats:italic>\n            arithmetic. We also present the implementation details of a parameterized and feature-complete\n            <jats:italic>posit<\/jats:italic>\n            Floating Point Unit (FPU). The configurability and the parameterization features of this unit generate optimal hardware, which caters to the accuracy and energy\/area tradeoffs imposed by the applications, a feature not possible with IEEE-754 implementation. The\n            <jats:italic>posit<\/jats:italic>\n            FPU has been integrated with the RISC-V compliant SHAKTI C-class core as an execution unit. To further leverage the potential of\n            <jats:italic>posit<\/jats:italic>\n            , we enhance our\n            <jats:italic>posit<\/jats:italic>\n            FPU to support two different exponent sizes (with posit-size being 32-bits), thereby enabling multiple-precision at runtime. To enable the compilation and execution of C programs on PERI, we have made minimal modifications to the GNU C Compiler (GCC), targeting the \u201cF\u201d extension of the RISC-V. We compare\n            <jats:italic>posit<\/jats:italic>\n            with IEEE-754 in terms of hardware area, application accuracy, and runtime. We also present an alternate methodology of integrating the\n            <jats:italic>posit<\/jats:italic>\n            FPU with the RISC-V core as an accelerator using the custom opcode space of RISC-V.\n          <\/jats:p>","DOI":"10.1145\/3446210","type":"journal-article","created":{"date-parts":[[2021,4,14]],"date-time":"2021-04-14T19:37:51Z","timestamp":1618429071000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":32,"title":["PERI"],"prefix":"10.1145","volume":"18","author":[{"given":"Sugandha","family":"Tiwari","sequence":"first","affiliation":[{"name":"Indian Institute of Technology Madras, India"}]},{"given":"Neel","family":"Gala","sequence":"additional","affiliation":[{"name":"InCore Semiconductors Pvt. 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