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Embed. Comput. Syst."],"published-print":{"date-parts":[[2021,7,31]]},"abstract":"<jats:p>Hardware Trojan (HT) is a major threat to the security of integrated circuits (ICs). Among various HT detection approaches, side channel analysis (SCA)-based methods have been extensively studied. SCA-based methods try to detect HTs by comparing side channel signatures from circuits under test with those from trusted golden references. The pre-condition for SCA-based HT detection to work is that the testers can collect extra signatures\/anomalies introduced by activated HTs. Thus, activation of HTs and amplification of the differences between circuits under test and golden references are the keys to SCA-based HT detection methods. Test vectors are of great importance to the activation of HTs, but existing test generation methods have two major limitations. First, the number of test vectors required to trigger HTs is quite large. Second, the HT circuit\u2019s activities are marginal compared with the whole circuit\u2019s activities. In this article, we propose an optimized test generation methodology to assist SCA-based HT detection. Considering the HTs\u2019 inherent surreptitious nature, inactive nodes with low transition probability are more likely to be selected as HT trigger nodes. Therefore, the correlations between circuit inputs and inactive nodes are first exploited to activate HTs. Then a test reordering process based on the genetic algorithm (GA) is implemented to increase the proportion of the HT circuit\u2019s activities to the whole circuit\u2019s activities. Experiments on 10 selected ISCAS benchmarks, wb_conmax benchmark, and b17 benchmark demonstrate that the number of test vectors required to trigger HTs reduces 28.8% on average compared with the result of MERO and MERS methods. After the test vector reordering process, the proportion of the HT circuit\u2019s activities to the whole circuit\u2019s activities is improved by 95% on average, compared with the result of MERS method.<\/jats:p>","DOI":"10.1145\/3446837","type":"journal-article","created":{"date-parts":[[2021,3,26]],"date-time":"2021-03-26T16:31:01Z","timestamp":1616776261000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":17,"title":["Test Generation for Hardware Trojan Detection Using Correlation Analysis and Genetic Algorithm"],"prefix":"10.1145","volume":"20","author":[{"given":"Zhendong","family":"Shi","sequence":"first","affiliation":[{"name":"School of Microelectronics, Tianjin University, Tianjin Shi, China"}]},{"given":"Haocheng","family":"Ma","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Tianjin University, Tianjin Shi, China"}]},{"given":"Qizhi","family":"Zhang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Tianjin University, Tianjin Shi, China"}]},{"given":"Yanjiang","family":"Liu","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Tianjin University, Tianjin Shi, China"}]},{"given":"Yiqiang","family":"Zhao","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Tianjin University, Tianjin Shi, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1443-9279","authenticated-orcid":false,"given":"Jiaji","family":"He","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Tsinghua University, Beijing Shi, China"}]}],"member":"320","published-online":{"date-parts":[[2021,3,26]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1387328"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2424929"},{"key":"e_1_2_1_3_1","unstructured":"ISCAS benchmark circuits. 2007. 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