{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,12]],"date-time":"2025-08-12T21:39:03Z","timestamp":1755034743532,"version":"3.41.0"},"reference-count":45,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2021,4,14]],"date-time":"2021-04-14T00:00:00Z","timestamp":1618358400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100013209","name":"Hellenic Foundation for Research and Innovation","doi-asserted-by":"publisher","award":["81708"],"award-info":[{"award-number":["81708"]}],"id":[{"id":"10.13039\/501100013209","id-type":"DOI","asserted-by":"publisher"}]},{"name":"General Secretariat forResearch and Technology","award":["81708"],"award-info":[{"award-number":["81708"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2021,9,30]]},"abstract":"<jats:p>\n            Executing complex scientific applications on Coarse-Grain Reconfigurable Arrays (\n            <jats:bold>CGRAs<\/jats:bold>\n            ) promises improvements in execution time and\/or energy consumption compared to optimized software implementations or even fully customized hardware solutions. Typical CGRA architectures contain of multiple instances of the same compute module that consist of simple and general hardware units such as ALUs, simple processors. However, generality in the cell contents, while convenient for serving a wide variety of applications, penalizes performance and energy efficiency. To that end, a few proposed CGRAs use custom logic tailored to a particular application\u2019s specific characteristics in the compute module. This approach, while much more efficient, restricts the versatility of the array. To date, versatility at hardware speeds is only supported with Field programmable gate arrays (FPGAs), that are reconfigurable at a very fine grain.\n          <\/jats:p>\n          <jats:p>This work proposes MC-DeF, a novel Mixed-CGRA Definition Framework targeting a Mixed-CGRA architecture that leverages the advantages of CGRAs by utilizing a customized cell array, and those of FPGAs by incorporating a separate LUT array used for adaptability. The framework presented aims to develop a complete CGRA architecture. First, a cell structure and functionality definition phase creates highly customized application\/domain specific CGRA cells. Then, mapping and routing phases define the CGRA connectivity and cell-LUT array transactions. Finally, an energy and area estimation phase presents the user with area occupancy and energy consumption estimations of the final design. MC-DeF uses novel algorithms and cost functions driven by user defined metrics, threshold values, and area\/energy restrictions. The benefits of our framework, besides creating fast and efficient CGRA designs, include design space exploration capabilities offered to the user.<\/jats:p>\n          <jats:p>The validity of the presented framework is demonstrated by evaluating and creating CGRA designs of nine applications. Additionally, we provide comparisons of MC-DeF with state-of-the-art related works, and show that MC-DeF offers competitive performance (in terms of internal bandwidth and processing throughput) even compared against much larger designs, and requires fewer physical resources to achieve this level of performance. Finally, MC-DeF is able to better utilize the underlying FPGA fabric and achieves the best efficiency (measured in LUT\/GOPs).<\/jats:p>","DOI":"10.1145\/3447970","type":"journal-article","created":{"date-parts":[[2021,4,14]],"date-time":"2021-04-14T19:37:51Z","timestamp":1618429071000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["MC-DeF"],"prefix":"10.1145","volume":"18","author":[{"given":"George","family":"Charitopoulos","sequence":"first","affiliation":[{"name":"School of Electrical and Computer Engineering, Technical University of Crete, Akrotiri Chania, Greece"}]},{"given":"Dionisios N.","family":"Pnevmatikatos","sequence":"additional","affiliation":[{"name":"School of Electric and Computer Engineering, National Technical University of Athens"}]},{"given":"Georgi","family":"Gaydadjiev","sequence":"additional","affiliation":[{"name":"Bernoulli Institute, University of Groningen and Department of Computing, Imperial College London"}]}],"member":"320","published-online":{"date-parts":[[2021,4,14]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1596543.1596545"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2044667"},{"key":"e_1_2_1_4_1","volume-title":"2017 IEEE International Solid-State Circuits Conference (ISSCC\u201917)","author":"\u00a0al J. Chang","year":"2017","unstructured":"J. Chang et \u00a0al . 2017 . 12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications . In 2017 IEEE International Solid-State Circuits Conference (ISSCC\u201917) . 206--207. J. Chang et\u00a0al. 2017. 12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. In 2017 IEEE International Solid-State Circuits Conference (ISSCC\u201917). 206--207."},{"volume-title":"18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS\u201918)","author":"Charitopoulos George","key":"e_1_2_1_5_1","unstructured":"George Charitopoulos and Dionisios N. Pnevmatikatos . 2018. DARSA: A dataflow analysis tool for reconfigurable platforms . In 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS\u201918) . 65--72. George Charitopoulos and Dionisios N. Pnevmatikatos. 2018. DARSA: A dataflow analysis tool for reconfigurable platforms. In 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS\u201918). 65--72."},{"key":"e_1_2_1_6_1","volume-title":"Pnevmatikatos","author":"Charitopoulos George","year":"2020","unstructured":"George Charitopoulos and Dionisios N . Pnevmatikatos . 2020 . A CGRA definition framework for dataflow applications. In Applied Reconfigurable Computing. Springer International Publishing , Cham. George Charitopoulos and Dionisios N. Pnevmatikatos. 2020. A CGRA definition framework for dataflow applications. In Applied Reconfigurable Computing. Springer International Publishing, Cham."},{"key":"e_1_2_1_7_1","volume-title":"2017 IEEE 28th International Conference on Application-Specific Systems, Architectures and Processors (ASAP\u201917)","author":"Chin S. A.","year":"2017","unstructured":"S. A. Chin , N. Sakamoto , A. Rui , J. Zhao , J. H. Kim , Y. Hara-Azumi , and J. Anderson . 2017. CGRA-ME: A unified framework for CGRA modelling and exploration . In 2017 IEEE 28th International Conference on Application-Specific Systems, Architectures and Processors (ASAP\u201917) . 184--189. DOI:https:\/\/doi.org\/10.1109\/ASAP. 2017 .7995277 S. A. Chin, N. Sakamoto, A. Rui, J. Zhao, J. H. Kim, Y. Hara-Azumi, and J. Anderson. 2017. CGRA-ME: A unified framework for CGRA modelling and exploration. In 2017 IEEE 28th International Conference on Application-Specific Systems, Architectures and Processors (ASAP\u201917). 184--189. DOI:https:\/\/doi.org\/10.1109\/ASAP.2017.7995277"},{"key":"e_1_2_1_8_1","volume-title":"36th Annual IEEE\/ACM International Symposium on Microarchitecture","author":"Clark N.","year":"2003","unstructured":"N. Clark , Hongtao Zhong , and S. Mahlke . 2003. Processor acceleration through automated instruction set customization . In 36th Annual IEEE\/ACM International Symposium on Microarchitecture , 2003 . MICRO-36. 129--140. N. Clark, Hongtao Zhong, and S. Mahlke. 2003. Processor acceleration through automated instruction set customization. In 36th Annual IEEE\/ACM International Symposium on Microarchitecture, 2003. MICRO-36. 129--140."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.12"},{"volume-title":"2010 IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201910)","author":"Coole J.","key":"e_1_2_1_10_1","unstructured":"J. Coole and G. Stitt . 2010. Intermediate fabrics: Virtual architectures for circuit portability and fast placement and routing . In 2010 IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201910) . 13--22. J. Coole and G. Stitt. 2010. Intermediate fabrics: Virtual architectures for circuit portability and fast placement and routing. In 2010 IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201910). 13--22."},{"key":"e_1_2_1_11_1","volume-title":"Challenges for Future Computing Systems. Presentation in HiPEAC Conference.","author":"Dally Bill","year":"2015","unstructured":"Bill Dally . 2015 . Challenges for Future Computing Systems. Presentation in HiPEAC Conference. Bill Dally. 2015. Challenges for Future Computing Systems. Presentation in HiPEAC Conference."},{"volume-title":"Handbook of Signal Processing Systems","author":"Sutter Bjorn De","key":"e_1_2_1_12_1","unstructured":"Bjorn De Sutter , Praveen Raghavan , and Andy Lambrechts . 2019. Coarse-grained reconfigurable array architectures . In Handbook of Signal Processing Systems . Springer , 427--472. Bjorn De Sutter, Praveen Raghavan, and Andy Lambrechts. 2019. Coarse-grained reconfigurable array architectures. In Handbook of Signal Processing Systems. Springer, 427--472."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-61730-2_13"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.14778\/2732286.2732289"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.51"},{"volume-title":"2011 IEEE 17th International Symposium on High Performance Computer Architecture. 503--514","author":"Govindaraju V.","key":"e_1_2_1_16_1","unstructured":"V. Govindaraju , C. Ho , and K. Sankaralingam . 2011. Dynamically specialized datapaths for energy efficient computing . In 2011 IEEE 17th International Symposium on High Performance Computer Architecture. 503--514 . V. Govindaraju, C. Ho, and K. Sankaralingam. 2011. Dynamically specialized datapaths for energy efficient computing. In 2011 IEEE 17th International Symposium on High Performance Computer Architecture. 503--514."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370535"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.3150\/bj\/1116340299"},{"key":"e_1_2_1_19_1","volume-title":"Seung Eun Lee, and Nader Bagherzadeh","author":"Hu Wen-Hsiang","year":"2008","unstructured":"Wen-Hsiang Hu , Seung Eun Lee, and Nader Bagherzadeh . 2008 . DMesh: A diagonally-linked mesh network-on-chip architecture. Network on Chip Architectures ( 2008), 14. Wen-Hsiang Hu, Seung Eun Lee, and Nader Bagherzadeh. 2008. DMesh: A diagonally-linked mesh network-on-chip architecture. Network on Chip Architectures (2008), 14."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3229631.3229635"},{"volume-title":"2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines. 165--168","author":"Jacobsen M.","key":"e_1_2_1_21_1","unstructured":"M. Jacobsen , P. Meng , S. Sampangi , and R. Kastner . 2014. FPGA accelerated online boosting for multi-target tracking . In 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines. 165--168 . M. Jacobsen, P. Meng, S. Sampangi, and R. Kastner. 2014. FPGA accelerated online boosting for multi-target tracking. In 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines. 165--168."},{"volume-title":"2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines. 25--28","author":"Jain A. K.","key":"e_1_2_1_22_1","unstructured":"A. K. Jain , S. A. Fahmy , and D. L. Maskell . 2015. Efficient overlay architecture based on DSP blocks . In 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines. 25--28 . A. K. Jain, S. A. Fahmy, and D. L. Maskell. 2015. Efficient overlay architecture based on DSP blocks. In 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines. 25--28."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2927964.2927970"},{"volume-title":"2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201916)","author":"Jain A. K.","key":"e_1_2_1_24_1","unstructured":"A. K. Jain , X. Li , P. Singhai , D. L. Maskell , and S. A. Fahmy . 2016. DeCO: A DSP block based FPGA accelerator overlay with low overhead interconnect . In 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201916) . 1--8. A. K. Jain, X. Li, P. Singhai, D. L. Maskell, and S. A. Fahmy. 2016. DeCO: A DSP block based FPGA accelerator overlay with low overhead interconnect. In 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201916). 1--8."},{"volume-title":"2016 IEEE 14th International Conference on Dependable, Autonomic and Secure Computing, 14th International Conference on Pervasive Intelligence and Computing (DASC\/PiCom\/DataCom\/CyberSciTech\u201916)","author":"Jain A. K.","key":"e_1_2_1_25_1","unstructured":"A. K. Jain , D. L. Maskell , and S. A. Fahmy . 2016. Are coarse-grained overlays ready for general purpose application acceleration on FPGAs? In 2016 IEEE 14th International Conference on Dependable, Autonomic and Secure Computing, 14th International Conference on Pervasive Intelligence and Computing (DASC\/PiCom\/DataCom\/CyberSciTech\u201916) . 586--593. A. K. Jain, D. L. Maskell, and S. A. Fahmy. 2016. Are coarse-grained overlays ready for general purpose application acceleration on FPGAs? In 2016 IEEE 14th International Conference on Dependable, Autonomic and Secure Computing, 14th International Conference on Pervasive Intelligence and Computing (DASC\/PiCom\/DataCom\/CyberSciTech\u201916). 586--593."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.89"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2380403.2380427"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2015.7393130"},{"key":"e_1_2_1_30_1","volume-title":"2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines. 228--228","author":"Liu C.","year":"2013","unstructured":"C. Liu , C. L. Yu , and H. K. So . 2013. A soft coarse-grained reconfigurable array based high-level synthesis methodology: Promoting design productivity and exploring extreme FPGA frequency . In 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines. 228--228 . DOI:https:\/\/doi.org\/10.1109\/FCCM. 2013 .21 C. Liu, C. L. Yu, and H. K. So. 2013. A soft coarse-grained reconfigurable array based high-level synthesis methodology: Promoting design productivity and exploring extreme FPGA frequency. In 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines. 228--228. DOI:https:\/\/doi.org\/10.1109\/FCCM.2013.21"},{"key":"e_1_2_1_31_1","volume-title":"Data-flow graph mapping optimization for CGRA with deep reinforcement learning","author":"\u00a0al D. Liu","year":"2018","unstructured":"D. Liu et \u00a0al . 2018. Data-flow graph mapping optimization for CGRA with deep reinforcement learning . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( 2018 ), 1--1. D. Liu et\u00a0al. 2018. Data-flow graph mapping optimization for CGRA with deep reinforcement learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2018), 1--1."},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847341"},{"volume-title":"IEEE 17th International Conference on High Performance Computing and Communications, and 12th International Conference on Embedded Software and Systems. 405--410","author":"Madhu K. T.","key":"e_1_2_1_33_1","unstructured":"K. T. Madhu , S. Das , S. Nalesh , S. K. Nandy , and R. Narayan . 2015. Compiling HPC kernels for the REDEFINE CGRA . In IEEE 17th International Conference on High Performance Computing and Communications, and 12th International Conference on Embedded Software and Systems. 405--410 . K. T. Madhu, S. Das, S. Nalesh, S. K. Nandy, and R. Narayan. 2015. Compiling HPC kernels for the REDEFINE CGRA. In IEEE 17th International Conference on High Performance Computing and Communications, and 12th International Conference on Embedded Software and Systems. 405--410."},{"key":"e_1_2_1_34_1","volume-title":"Smit","author":"Niedermeier A.","year":"2014","unstructured":"A. Niedermeier , Jan Kuper , and Gerard J. M . Smit . 2014 . A dataflow inspired programming paradigm for coarse-grained reconfigurable arrays. In Reconfigurable Computing: Architectures, Tools, and Applications. Springer International Publishing , Cham, 275--282. A. Niedermeier, Jan Kuper, and Gerard J. M. Smit. 2014. A dataflow inspired programming paradigm for coarse-grained reconfigurable arrays. In Reconfigurable Computing: Architectures, Tools, and Applications. Springer International Publishing, Cham, 275--282."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2012.78"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2015.7477325"},{"key":"e_1_2_1_37_1","first-page":"1","article-title":"Dataflow-based mapping of computer vision algorithms onto FPGAs","volume":"2007","author":"\u00a0al Mainak Sen","year":"2007","unstructured":"Mainak Sen et \u00a0al . 2007 . Dataflow-based mapping of computer vision algorithms onto FPGAs . EURASIP Journal on Embedded Systems 2007 , 1 (Jan. 2007), 049236. Mainak Sen et\u00a0al. 2007. Dataflow-based mapping of computer vision algorithms onto FPGAs. EURASIP Journal on Embedded Systems 2007, 1 (Jan. 2007), 049236.","journal-title":"EURASIP Journal on Embedded Systems"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2013.2243698"},{"key":"e_1_2_1_39_1","volume-title":"2016 IEEE International Interconnect Technology Conference\/Advanced Metallization Conference (IITC\/AMC\u201916)","author":"\u00a0al T. Standaert","year":"2016","unstructured":"T. Standaert et \u00a0al . 2016 . BEOL process integration for the 7 nm technology node . In 2016 IEEE International Interconnect Technology Conference\/Advanced Metallization Conference (IITC\/AMC\u201916) . 2--4. T. Standaert et\u00a0al. 2016. BEOL process integration for the 7 nm technology node. In 2016 IEEE International Interconnect Technology Conference\/Advanced Metallization Conference (IITC\/AMC\u201916). 2--4."},{"key":"e_1_2_1_40_1","first-page":"5","article-title":"Selective flexibility: Creating domain-specific reconfigurable arrays","volume":"32","author":"M. Stojilovi","year":"2013","unstructured":"M. Stojilovi \u0107, D. Novo , L. Saranovac , P. Brisk , and P. Ienne . 2013 . Selective flexibility: Creating domain-specific reconfigurable arrays . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32 , 5 (May 2013), 681--694. M. Stojilovi \u0107, D. Novo, L. Saranovac, P. Brisk, and P. Ienne. 2013. Selective flexibility: Creating domain-specific reconfigurable arrays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, 5 (May 2013), 681--694.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00054"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1186\/s40537-015-0038-8"},{"volume-title":"2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems. 92--97","author":"Varma B. S. C.","key":"e_1_2_1_43_1","unstructured":"B. S. C. Varma , K. Paul , and M. Balakrishnan . 2013. Accelerating 3D-FFT using hard embedded blocks in FPGAs . In 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems. 92--97 . B. S. C. Varma, K. Paul, and M. Balakrishnan. 2013. Accelerating 3D-FFT using hard embedded blocks in FPGAs. In 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems. 92--97."},{"issue":"6","key":"e_1_2_1_44_1","article-title":"7 Series FPGAs Data Sheet","volume":"2","author":"Xilinx","year":"2018","unstructured":"Xilinx 2018 . 7 Series FPGAs Data Sheet : Overview. Xilinx. Rev. 2 . 6 . Xilinx 2018. 7 Series FPGAs Data Sheet: Overview. Xilinx. Rev. 2.6.","journal-title":"Overview. Xilinx. Rev."},{"volume-title":"2017 IEEE International Symposium on Circuits and Systems (ISCAS\u201917)","author":"Yin S.","key":"e_1_2_1_45_1","unstructured":"S. Yin , D. Liu , L. Sun , L. Liu , and S. Wei . 2017. DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach . In 2017 IEEE International Symposium on Circuits and Systems (ISCAS\u201917) . 1--4. S. Yin, D. Liu, L. Sun, L. Liu, and S. Wei. 2017. DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach. In 2017 IEEE International Symposium on Circuits and Systems (ISCAS\u201917). 1--4."}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3447970","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3447970","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:28:24Z","timestamp":1750195704000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3447970"}},"subtitle":["Creating Customized CGRAs for Dataflow Applications"],"short-title":[],"issued":{"date-parts":[[2021,4,14]]},"references-count":45,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2021,9,30]]}},"alternative-id":["10.1145\/3447970"],"URL":"https:\/\/doi.org\/10.1145\/3447970","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"type":"print","value":"1544-3566"},{"type":"electronic","value":"1544-3973"}],"subject":[],"published":{"date-parts":[[2021,4,14]]},"assertion":[{"value":"2020-07-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-01-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-04-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}