{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,29]],"date-time":"2025-10-29T06:25:18Z","timestamp":1761719118819,"version":"3.41.0"},"reference-count":46,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2021,12,31]],"date-time":"2021-12-31T00:00:00Z","timestamp":1640908800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100002322","name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior - Brasil","doi-asserted-by":"crossref","award":["001"],"award-info":[{"award-number":["001"]}],"id":[{"id":"10.13039\/501100002322","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100003593","name":"National Council for Scientific and Technological Development","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100003593","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Deutscher Akademischer Austauschdienst"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2022,4,30]]},"abstract":"<jats:p>\n            Accelerating finite-state automata benefits several emerging application domains that are built on pattern matching. In-memory architectures, such as the Automata Processor (AP), are efficient to speed them up, at least for outperforming traditional von-Neumann architectures. In spite of the AP\u2019s massive parallelism, current APs suffer from poor memory density, inefficient routing architectures, and limited capabilities. Although these limitations can be lessened by emerging memory technologies, its architecture is still the major source of huge communication demands and lack of scalability. To address these issues, we present\n            <jats:bold>STAP<\/jats:bold>\n            , a\n            <jats:bold>Scalable TCAM-based architecture for Automata Processing<\/jats:bold>\n            . STAP adopts a reconfigurable array of processing elements, which are based on memristive Ternary CAMs (TCAMs), to efficiently implement Non-deterministic finite automata (NFAs) through proper encoding and mapping methods. The CAD tool for STAP integrates the design flow of automata applications, a specific mapping algorithm, and place and route tools for connecting processing elements by RRAM-based programmable interconnects. Results showed 1.47\u00d7 higher throughput when processing 16-bit input symbols, and improvements of 3.9\u00d7 and 25\u00d7 on state and routing densities over the state-of-the-art AP, while preserving 10\n            <jats:sup>4<\/jats:sup>\n            programming cycles.\n          <\/jats:p>","DOI":"10.1145\/3450769","type":"journal-article","created":{"date-parts":[[2021,12,31]],"date-time":"2021-12-31T14:34:17Z","timestamp":1640961257000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["STAP: An Architecture and Design Tool for Automata Processing on Memristor TCAMs"],"prefix":"10.1145","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9295-3519","authenticated-orcid":false,"given":"Jo\u00e3o Paulo Cardoso","family":"de Lima","sequence":"first","affiliation":[{"name":"Federal University of Rio Grande do Sul, Porto Alegre, Rio Grande do Sul, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0012-7023","authenticated-orcid":false,"given":"Marcelo","family":"Brandalero","sequence":"additional","affiliation":[{"name":"Brandenburg University of Technology, Cottbus, Bradenburg, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1790-3869","authenticated-orcid":false,"given":"Michael","family":"H\u00fcbner","sequence":"additional","affiliation":[{"name":"Brandenburg University of Technology, Cottbus, Bradenburg, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7402-4780","authenticated-orcid":false,"given":"Luigi","family":"Carro","sequence":"additional","affiliation":[{"name":"Federal University of Rio Grande do Sul, Porto Alegre, Rio Grande do Sul, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2021,12,31]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/1185347.1185360"},{"key":"e_1_3_2_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2014.8"},{"key":"e_1_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCBB.2015.2430313"},{"key":"e_1_3_2_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00068"},{"key":"e_1_3_2_6_2","article-title":"Entity resolution acceleration using Micron\u2019s automata processor","author":"Bo Chunkun","year":"2015","unstructured":"Chunkun Bo, Ke Wang, Jeffrey J. Fox, and Kevin Skadron. 2015. Entity resolution acceleration using Micron\u2019s automata processor. Proceedings of Architectures and Systems for Big Data (ASBD), in Conjunction with ISCA (2015).","journal-title":"Proceedings of Architectures and Systems for Big Data (ASBD), in Conjunction with ISCA"},{"key":"e_1_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/BigData.2017.8257936"},{"key":"e_1_3_2_8_2","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080207"},{"key":"e_1_3_2_9_2","doi-asserted-by":"publisher","DOI":"10.1145\/3314576"},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/BigData.2015.7363776"},{"key":"e_1_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/3219819.3219889"},{"key":"e_1_3_2_12_2","article-title":"Micron accelerates automata: New chip speeds NFA processing using DRAM architectures","author":"Gwennap Linley","year":"2014","unstructured":"Linley Gwennap. 2014. Micron accelerates automata: New chip speeds NFA processing using DRAM architectures. Microprocessor Report (2014).","journal-title":"Microprocessor Report"},{"key":"e_1_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123986"},{"key":"e_1_3_2_14_2","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358324"},{"key":"e_1_3_2_15_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715140"},{"key":"e_1_3_2_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2019.2902359"},{"key":"e_1_3_2_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2017.12"},{"key":"e_1_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358324"},{"key":"e_1_3_2_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2017.38"},{"key":"e_1_3_2_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2018.2822862"},{"key":"e_1_3_2_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2259512"},{"key":"e_1_3_2_22_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342278"},{"key":"e_1_3_2_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2805470"},{"key":"e_1_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.1063\/1.5129101"},{"key":"e_1_3_2_25_2","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2909317"},{"key":"e_1_3_2_26_2","doi-asserted-by":"publisher","DOI":"10.3390\/make1010005"},{"key":"e_1_3_2_27_2","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155660"},{"key":"e_1_3_2_28_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2015.7293982"},{"key":"e_1_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2019.2936239"},{"key":"e_1_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.1002\/adma.202003437"},{"key":"e_1_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2018.8573482"},{"key":"e_1_3_2_32_2","doi-asserted-by":"publisher","DOI":"10.5555\/1929820.1929831"},{"key":"e_1_3_2_33_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"e_1_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM48280.2020.00027"},{"key":"e_1_3_2_35_2","volume-title":"VASim: An Open Virtual Automata Simulator for Automata Processing Application and Architecture Research","author":"Wadden Jack","year":"2016","unstructured":"Jack Wadden and Kevin Skadron. 2016. VASim: An Open Virtual Automata Simulator for Automata Processing Application and Architecture Research. Technical Report CS2016-03. University of Virginia."},{"key":"e_1_3_2_36_2","doi-asserted-by":"publisher","DOI":"10.1145\/2068716.2068718"},{"key":"e_1_3_2_37_2","doi-asserted-by":"publisher","DOI":"10.1145\/2370036.2145833"},{"key":"e_1_3_2_38_2","doi-asserted-by":"publisher","DOI":"10.1145\/2318857.2254802"},{"key":"e_1_3_2_39_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"e_1_3_2_40_2","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378459"},{"key":"e_1_3_2_41_2","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2017.8252610"},{"key":"e_1_3_2_42_2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2019.2894387"},{"key":"e_1_3_2_43_2","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056759"},{"key":"e_1_3_2_44_2","first-page":"1","volume-title":"2016 IEEE International Symposium on Workload Characterization (IISWC)","author":"Wadden Jack","year":"2016","unstructured":"Jack Wadden, Vinh Dang, Nathan Brunelle, Tommy Tracy II, Deyuan Guo, Elaheh Sadredini, Ke Wang, Chunkun Bo, Gabriel Robins, and Mircea Stan. 2016. ANMLzoo: A benchmark suite for exploring bottlenecks in automata processing engines and architectures. In 2016 IEEE International Symposium on Workload Characterization (IISWC). IEEE, 1\u201312."},{"key":"e_1_3_2_45_2","doi-asserted-by":"publisher","DOI":"10.1109\/ANCS.2011.13"},{"key":"e_1_3_2_46_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2671408"},{"key":"e_1_3_2_47_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCCN.2018.8487404"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3450769","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3450769","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:28:42Z","timestamp":1750195722000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3450769"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12,31]]},"references-count":46,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2022,4,30]]}},"alternative-id":["10.1145\/3450769"],"URL":"https:\/\/doi.org\/10.1145\/3450769","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2021,12,31]]},"assertion":[{"value":"2020-08-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-02-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-12-31","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}