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Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2022,4,30]]},"abstract":"<jats:p>\n            Conventional von Neumann architectures cannot successfully meet the demands of emerging computation and data-intensive applications. These shortcomings can be improved by embracing new architectural paradigms using emerging technologies. In particular,\n            <jats:italic>Computation-In-Memory (CiM)<\/jats:italic>\n            using emerging technologies such as\n            <jats:italic>Resistive Random Access Memory (ReRAM)<\/jats:italic>\n            is a promising approach to meet the computational demands of data-intensive applications such as neural networks and database queries. In CiM, computation is done in an analog manner; digitization of the results is costly in several aspects, such as area, energy, and performance, which hinders the potential of CiM. In this article, we propose an efficient Voltage-Controlled-Oscillator (VCO)\u2013based analog-to-digital converter (ADC) design to improve the performance and energy efficiency of the CiM architecture. Due to its efficiency, the proposed ADC can be assigned in a per-column manner instead of sharing one ADC among multiple columns. This will boost the parallel execution and overall efficiency of the CiM crossbar array. The proposed ADC is evaluated using a Multiplication and Accumulation (MAC) operation implemented in ReRAM-based CiM crossbar arrays. Simulations results show that our proposed ADC can distinguish up to 32 levels within 10\u00a0ns while consuming less than 5.2\u00a0pJ of energy. In addition, our proposed ADC can tolerate \u224830% variability with a negligible impact on the performance of the ADC.\n          <\/jats:p>","DOI":"10.1145\/3451212","type":"journal-article","created":{"date-parts":[[2022,3,26]],"date-time":"2022-03-26T05:40:55Z","timestamp":1648273255000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":17,"title":["A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs"],"prefix":"10.1145","volume":"18","author":[{"given":"Mahta","family":"Mayahinia","sequence":"first","affiliation":[{"name":"Delft University of Technology, Delft, Netherlands"}]},{"given":"Abhairaj","family":"Singh","sequence":"additional","affiliation":[{"name":"Delft University of Technology, Delft, Netherlands"}]},{"given":"Christopher","family":"Bengel","sequence":"additional","affiliation":[{"name":"RWTH Aachen University, Aachen, Germany"}]},{"given":"Stefan","family":"Wiefels","sequence":"additional","affiliation":[{"name":"RWTH Aachen University, Aachen, Germany"}]},{"given":"Muath A.","family":"Lebdeh","sequence":"additional","affiliation":[{"name":"Delft University of Technology, Delft, Netherlands"}]},{"given":"Stephan","family":"Menzel","sequence":"additional","affiliation":[{"name":"Forschungszentrum Juelich GmbH, Peter-Gruenberg Institut (PGI-7), Juelich, Germany"}]},{"given":"Dirk J.","family":"Wouters","sequence":"additional","affiliation":[{"name":"RWTH Aachen University, Aachen, Germany"}]},{"given":"Anteneh","family":"Gebregiorgis","sequence":"additional","affiliation":[{"name":"Delft University of Technology, Delft, Netherlands"}]},{"given":"Rajendra","family":"Bishnoi","sequence":"additional","affiliation":[{"name":"Delft University of Technology, Delft, Netherlands"}]},{"given":"Rajiv","family":"Joshi","sequence":"additional","affiliation":[{"name":"IBM Thomas J. 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