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To improve system performance, cost, and energy efficiency, vertical-optimization in multiple layers of the computing stack is required. Technological awareness in terms of devices and circuits could enable informed system-level decisions. For example, graphene is a promising material for extremely scaled high-speed transistors because of its remarkably high mobility, but it can not be used in integrated circuits as a result of the high leakage current from its zero bandgap. In this article, we discuss the fundamental physics of transistors and their ramifications on system design to assist device-level technology consideration during system design. Additionally, various emerging devices and their utilization on a vertically-optimized computing stack are introduced. This article serves as a survey of emerging device technologies that may be relevant in these areas, with an emphasis on making the descriptions approachable by system and software designers to understand the potential solutions. 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Advanced 3D monolithic hybrid CMOS with sub-50 nm gate inverters featuring replacement metal gate (RMG)-InGaAs nFETs on SiGe-OI fin pFETs. In Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201915). IEEE, 8\u20138."},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268425"},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl034841q"},{"key":"e_1_2_1_47_1","volume-title":"Monatomic Two-Dimensional Layers","author":"D\u2019angelo Marie","unstructured":"Marie D\u2019angelo and Iwao Matsuda . 2019. Basics and families of monatomic layers: Single-layer 2D materials . In Monatomic Two-Dimensional Layers . Elsevier , 3\u201322. Marie D\u2019angelo and Iwao Matsuda. 2019. Basics and families of monatomic layers: Single-layer 2D materials. In Monatomic Two-Dimensional Layers. Elsevier, 3\u201322."},{"key":"e_1_2_1_48_1","unstructured":"Semiconductor Engineering. [n.d.]. Multiple patterning. Retrieved from https:\/\/semiengineering.com\/knowledge_centers\/manufacturing\/patterning\/multipatterning\/.  Semiconductor Engineering. [n.d.]. Multiple patterning. Retrieved from https:\/\/semiengineering.com\/knowledge_centers\/manufacturing\/patterning\/multipatterning\/."},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024723.2000108"},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757460"},{"key":"e_1_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl203701g"},{"key":"e_1_2_1_52_1","first-page":"1","article-title":"The digital universe in 2020: Big data, bigger digital shadows, and biggest growth in the far east. IDC iView","volume":"2007","author":"Gantz John","year":"2012","unstructured":"John Gantz and David Reinsel . 2012 . The digital universe in 2020: Big data, bigger digital shadows, and biggest growth in the far east. IDC iView : IDC Anal. Future 2007 , 2012 (2012), 1 \u2013 16 . John Gantz and David Reinsel. 2012. The digital universe in 2020: Big data, bigger digital shadows, and biggest growth in the far east. IDC iView: IDC Anal. Future 2007, 2012 (2012), 1\u201316.","journal-title":"IDC Anal. Future"},{"key":"e_1_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2406734"},{"key":"e_1_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00072"},{"key":"e_1_2_1_55_1","first-page":"41828","article-title":"Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication. Sci","volume":"7","author":"Habibpour Omid","year":"2017","unstructured":"Omid Habibpour , Zhongxia Simon He , Wlodek Strupinski , Niklas Rorsman , and Herbert Zirath . 2017 . Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication. Sci . Rep. 7 (2017), 41828 . Omid Habibpour, Zhongxia Simon He, Wlodek Strupinski, Niklas Rorsman, and Herbert Zirath. 2017. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication. Sci. Rep. 7 (2017), 41828.","journal-title":"Rep."},{"key":"e_1_2_1_56_1","unstructured":"Linden Harrison. 2006. An introduction to Depletion-mode MOSFETs. Retrieved from https:\/\/www.mikrocontroller.net\/attachment\/389314\/IntroDepletionModeMOSFET.pdf.  Linden Harrison. 2006. An introduction to Depletion-mode MOSFETs. Retrieved from https:\/\/www.mikrocontroller.net\/attachment\/389314\/IntroDepletionModeMOSFET.pdf."},{"key":"e_1_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.5555\/1999263"},{"key":"e_1_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/3282307"},{"key":"e_1_2_1_59_1","volume-title":"Yosi Stein et\u00a0al","author":"Hills Gage","year":"2019","unstructured":"Gage Hills , Christian Lau , Andrew Wright , Samuel Fuller , Mindy D. Bishop , Tathagata Srimani , Pritpal Kanhaiya , Rebecca Ho , Aya Amer , Yosi Stein et\u00a0al . 2019 . Modern microprocessor built from complementary carbon nanotube transistors. Nature 572, 7771 (2019), 595\u2013602. Gage Hills, Christian Lau, Andrew Wright, Samuel Fuller, Mindy D. Bishop, Tathagata Srimani, Pritpal Kanhaiya, Rebecca Ho, Aya Amer, Yosi Stein et\u00a0al. 2019. Modern microprocessor built from complementary carbon nanotube transistors. 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Data is the new Oil . In Proceedings of the ANA Sr. Marketer\u2019s Summit. Clive Humby. 2006. Data is the new Oil. In Proceedings of the ANA Sr. Marketer\u2019s Summit."},{"key":"e_1_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1115\/1.1579508"},{"key":"e_1_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.5555\/3199700.3199730"},{"key":"e_1_2_1_72_1","unstructured":"Intel. 2019. Intel Core i9-9900K Processor. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/products\/processors\/core\/i9-processors\/i9-9900k.html.  Intel. 2019. Intel Core i9-9900K Processor. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/products\/processors\/core\/i9-processors\/i9-9900k.html."},{"key":"e_1_2_1_73_1","volume-title":"Ionescu and Heike Riel","author":"Adrian","year":"2011","unstructured":"Adrian M. Ionescu and Heike Riel . 2011 . Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 7373 (2011), 329. Adrian M. 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Critical thickness for ferroelectricity in perovskite ultrathin films. Nature 422, 6931 (2003), 506\u2013509."},{"key":"e_1_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1250885"},{"key":"e_1_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2009.2028609"},{"key":"e_1_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00035"},{"key":"e_1_2_1_84_1","volume-title":"Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201917)","author":"Krivokapic Zoran","unstructured":"Zoran Krivokapic , U. Rana , R. Galatage , A. Razavieh , A. Aziz , J. Liu , J. Shi , H. J. Kim , R. Sporer , C. Serrao et\u00a0al. 2017. 14nm ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications . In Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201917) . IEEE, 15\u20131. Zoran Krivokapic, U. Rana, R. Galatage, A. Razavieh, A. Aziz, J. Liu, J. Shi, H. J. Kim, R. Sporer, C. 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Retrieved November 3, 2019 from https:\/\/www.modders-inc.com\/intel-core-i9-9900k-processor-review\/6\/."},{"key":"e_1_2_1_105_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2015.03.021"},{"key":"e_1_2_1_106_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0026-2714(01)00049-X"},{"key":"e_1_2_1_107_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.2976148"},{"key":"e_1_2_1_108_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378513"},{"key":"e_1_2_1_109_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.1021567"},{"key":"e_1_2_1_110_1","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2018.2804383"},{"key":"e_1_2_1_111_1","volume-title":"Proceedings of the 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era. IEEE, 1\u20136.","author":"Najari Montassar","unstructured":"Montassar Najari , Sebastien Fregonese , Cristell Maneux , Thomas Zimmer , Hassene Mnif , and N. Masmoudi . 2008. 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Neudeck David J. Spry and Liang-Yu Chen. 2016. First-order SPICE modeling of extreme-temperature 4H-SiC JFET integrated circuits. Additional Papers and Presentations. HiTEC 000263\u2013000271.  Philip G. Neudeck David J. Spry and Liang-Yu Chen. 2016. First-order SPICE modeling of extreme-temperature 4H-SiC JFET integrated circuits. Additional Papers and Presentations. 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In Materials Science Forum, Vol. 924 . Trans Tech Publications, 949\u2013952. David J. Spry, Philip G. Neudeck, Dorothy Lukco, Liang Yu Chen, Michael J. Krasowski, Norman F. Prokop, Carl W. Chang, and Glenn M. Beheim. 2018. Prolonged 500\u00b0C operation of 100+ transistor silicon carbide integrated circuits. In Materials Science Forum, Vol. 924. Trans Tech Publications, 949\u2013952."},{"key":"e_1_2_1_142_1","doi-asserted-by":"publisher","DOI":"10.1016\/0924-4247(92)80184-5"},{"key":"e_1_2_1_143_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2013.75"},{"key":"e_1_2_1_144_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342275"},{"key":"e_1_2_1_145_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2016.2570248"},{"key":"e_1_2_1_146_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.2890033"},{"key":"e_1_2_1_147_1","doi-asserted-by":"publisher","DOI":"10.5555\/2556161"},{"key":"e_1_2_1_148_1","volume-title":"Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201917","author":"Turkot B.","unstructured":"B. Turkot , S. Carson , and A. Lio . 2017. Continuing Moore\u2019s law with EUV lithography . In Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201917 . IEEE, 14\u20134. B. Turkot, S. Carson, and A. Lio. 2017. Continuing Moore\u2019s law with EUV lithography. In Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201917. IEEE, 14\u20134."},{"key":"e_1_2_1_149_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2010.10.022"},{"key":"e_1_2_1_150_1","doi-asserted-by":"publisher","DOI":"10.1038\/ncomms14948"},{"key":"e_1_2_1_151_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl302015v"},{"key":"e_1_2_1_152_1","unstructured":"Wikichip. 2019. Wikichip 4004\u2014Intel. Retrieved from https:\/\/en.wikichip.org\/wiki\/intel\/mcs-4\/4004.  Wikichip. 2019. Wikichip 4004\u2014Intel. Retrieved from https:\/\/en.wikichip.org\/wiki\/intel\/mcs-4\/4004."},{"key":"e_1_2_1_153_1","volume-title":"The Free Encyclopedia.","unstructured":"Wikipedia. 2019. Wikipedia , The Free Encyclopedia. Retrieved from https:\/\/en.wikipedia.org\/wiki\/Instructions_per_second. Wikipedia. 2019. Wikipedia, The Free Encyclopedia. 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Povey, Nikolay Petkov, Maryam Shayesteh, Dan O\u2019Connell, Justin D. Holmes, and Ray Duffy. 2014. Junctionless nanowire transistor fabricated with high mobility Ge channel. Rapid Res. Lett. 8, 1 (2014), 65\u201368.","journal-title":"Rapid Res. Lett."},{"key":"e_1_2_1_163_1","volume-title":"Serge Luryi","author":"Zetterling C.-M.","unstructured":"C.-M. Zetterling . 2013. Silicon carbide high-temperature electronics\u2014Is this rocket science? Future Trends in Microelectronics: Frontiers and Innovations , Serge Luryi , Jimmy Xu, and Alex Zaslavsky (Eds.). John Wiley & Sons , 102\u2013109. C.-M. Zetterling. 2013. Silicon carbide high-temperature electronics\u2014Is this rocket science? Future Trends in Microelectronics: Frontiers and Innovations, Serge Luryi, Jimmy Xu, and Alex Zaslavsky (Eds.). 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