{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T10:07:58Z","timestamp":1781258878960,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":49,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,6,18]],"date-time":"2021-06-18T00:00:00Z","timestamp":1623974400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,6,19]]},"DOI":"10.1145\/3453483.3454075","type":"proceedings-article","created":{"date-parts":[[2021,6,18]],"date-time":"2021-06-18T13:51:32Z","timestamp":1624024292000},"page":"756-771","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Reticle: a virtual machine for programming modern FPGAs"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7185-9128","authenticated-orcid":false,"given":"Luis","family":"Vega","sequence":"first","affiliation":[{"name":"University of Washington, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Joseph","family":"McMahan","sequence":"additional","affiliation":[{"name":"University of Washington, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Adrian","family":"Sampson","sequence":"additional","affiliation":[{"name":"Cornell University, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dan","family":"Grossman","sequence":"additional","affiliation":[{"name":"University of Washington, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Luis","family":"Ceze","sequence":"additional","affiliation":[{"name":"University of Washington, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2021,6,18]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Achronix. 2019. Speedster7t IP Component Library User Guide. UG086. https:\/\/www.achronix.com\/sites\/default\/files\/docs\/Speedster7t_IP_Component_Library_User_Guide_UG086.pdf  Achronix. 2019. Speedster7t IP Component Library User Guide. UG086. https:\/\/www.achronix.com\/sites\/default\/files\/docs\/Speedster7t_IP_Component_Library_User_Guide_UG086.pdf"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/318593.318663"},{"key":"e_1_3_2_1_3_1","unstructured":"Ananda Samajdar Tushar Garg Tushar Krishna and Nachiket Kapre. [n.d.]. Scaling the Cascades. https:\/\/git.uwaterloo.ca\/watcag-public\/fpga-cascades-rtl  Ananda Samajdar Tushar Garg Tushar Krishna and Nachiket Kapre. [n.d.]. Scaling the Cascades. https:\/\/git.uwaterloo.ca\/watcag-public\/fpga-cascades-rtl"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/289423.289440"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385965"},{"key":"e_1_3_2_1_7_1","volume-title":"Formal Verification of Hardware Synthesis","author":"Braibant Thomas","unstructured":"Thomas Braibant and Adam Chlipala . 2013. Formal Verification of Hardware Synthesis . In Computer Aided Verification, Natasha Sharygina and Helmut Veith (Eds.). Springer Berlin Heidelberg , Berlin, Heidelberg . 213\u2013228. isbn:978-3-642-39799-8 Thomas Braibant and Adam Chlipala. 2013. Formal Verification of Hardware Synthesis. In Computer Aided Verification, Natasha Sharygina and Helmut Veith (Eds.). Springer Berlin Heidelberg, Berlin, Heidelberg. 213\u2013228. isbn:978-3-642-39799-8"},{"key":"e_1_3_2_1_8_1","volume-title":"ABC: An Academic Industrial-Strength Verification Tool","author":"Brayton Robert","year":"2010","unstructured":"Robert Brayton and Alan Mishchenko . 2010 . ABC: An Academic Industrial-Strength Verification Tool . In Computer Aided Verification, Tayssir Touili, Byron Cook, and Paul Jackson (Eds.). Springer Berlin Heidelberg , Berlin, Heidelberg . 24\u201340. isbn:978-3-642-14295-6 Robert Brayton and Alan Mishchenko. 2010. ABC: An Academic Industrial-Strength Verification Tool. In Computer Aided Verification, Tayssir Touili, Byron Cook, and Paul Jackson (Eds.). Springer Berlin Heidelberg, Berlin, Heidelberg. 24\u201340. isbn:978-3-642-14295-6"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275132"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3110268"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"crossref","unstructured":"Philip Colangelo Nasibeh Nasiri Asit Mishra Eriko Nurvitadhi Martin Margala and Kevin Nealis. 2018. Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs. arxiv:1806.11547.  Philip Colangelo Nasibeh Nasiri Asit Mishra Eriko Nurvitadhi Martin Margala and Kevin Nealis. 2018. Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs. arxiv:1806.11547.","DOI":"10.1145\/3174243.3174999"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2997704"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/1792734.1792766"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.4230\/LIPIcs.ECOOP.2019.6"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385983"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00012"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00012"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2601097.2601174"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/800068.802148"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375310"},{"key":"e_1_3_2_1_21_1","unstructured":"Intel. 2020. Intel Agilex FPGA Architecture. https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/wp\/intel-agilex-fpgas-deliver-game-changing-combination-wp.pdf  Intel. 2020. Intel Agilex FPGA Architecture. https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/wp\/intel-agilex-fpgas-deliver-game-changing-combination-wp.pdf"},{"key":"e_1_3_2_1_22_1","unstructured":"Intel. 2020. Intel HLS Compiler: Fast Design Coding and Hardware. WP-01274. https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/wp\/wp-01274-intel-hls-compiler-fast-design-coding-and-hardware.pdf  Intel. 2020. Intel HLS Compiler: Fast Design Coding and Hardware. WP-01274. https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/wp\/wp-01274-intel-hls-compiler-fast-design-coding-and-hardware.pdf"},{"key":"e_1_3_2_1_23_1","unstructured":"Intel. 2020. Intel Stratix 10 Variable PrecisionDSP Blocks User Guide. UG-S10-DSP. https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/hb\/stratix-10\/ug-s10-dsp.pdf  Intel. 2020. Intel Stratix 10 Variable PrecisionDSP Blocks User Guide. UG-S10-DSP. https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/hb\/stratix-10\/ug-s10-dsp.pdf"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203780"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2997638"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/567067.567070"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/53990.54000"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/3296979.3192379"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1982.1653825"},{"key":"e_1_3_2_1_30_1","unstructured":"Lattice. 2020. sysDSP Usage Guide for Nexus Platform. Technical Note FPGA-TN-02096-1.1.  Lattice. 2020. sysDSP Usage Guide for Nexus Platform. Technical Note FPGA-TN-02096-1.1."},{"key":"e_1_3_2_1_31_1","volume-title":"RapidWright: Enabling Custom Crafted Implementations for FPGAs. In 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 133\u2013140","author":"Lavin C.","unstructured":"C. Lavin and A. Kaviani . 2018 . RapidWright: Enabling Custom Crafted Implementations for FPGAs. In 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 133\u2013140 . C. Lavin and A. Kaviani. 2018. RapidWright: Enabling Custom Crafted Implementations for FPGAs. In 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 133\u2013140."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3314221.3314622"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887925"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385974"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446712"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2004.1459818"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/2666356.2594339"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665678"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.2200\/S00060ED1V01Y200610DCS006"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2474363"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/141471.141563"},{"key":"e_1_3_2_1_42_1","volume-title":"Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning Problems. In 2019 29th International Conference on Field Programmable Logic and Applications (FPL). 342\u2013349","author":"Samajdar A.","unstructured":"A. Samajdar , T. Garg , T. Krishna , and N. Kapre . 2019 . Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning Problems. In 2019 29th International Conference on Field Programmable Logic and Applications (FPL). 342\u2013349 . A. Samajdar, T. Garg, T. Krishna, and N. Kapre. 2019. Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning Problems. In 2019 29th International Conference on Field Programmable Logic and Applications (FPL). 342\u2013349."},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3386024"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/800055.802026"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.4230\/LIPIcs.SNAPL.2019.7"},{"key":"e_1_3_2_1_46_1","unstructured":"Mike Turpin. 2003. The Dangers of Living with an X (bugs hidden in your Verilog). https:\/\/developer.arm.com\/documentation\/arp0009\/a\/  Mike Turpin. 2003. The Dangers of Living with an X (bugs hidden in your Verilog). https:\/\/developer.arm.com\/documentation\/arp0009\/a\/"},{"key":"e_1_3_2_1_47_1","unstructured":"Xilinx. 2020. UltraScale Architecture DSP Slice User Guide. UG579. https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug579-ultrascale-dsp.pdf  Xilinx. 2020. UltraScale Architecture DSP Slice User Guide. UG579. https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug579-ultrascale-dsp.pdf"},{"key":"e_1_3_2_1_48_1","unstructured":"Xilinx. 2020. Versal:The First Adaptive Compute Acceleration Platform (ACAP). WP505. https:\/\/www.xilinx.com\/support\/documentation\/white_papers\/wp505-versal-acap.pdf  Xilinx. 2020. Versal:The First Adaptive Compute Acceleration Platform (ACAP). WP505. https:\/\/www.xilinx.com\/support\/documentation\/white_papers\/wp505-versal-acap.pdf"},{"key":"e_1_3_2_1_49_1","volume-title":"Vitis Unified Software Development Platform","year":"2020","unstructured":"Xilinx. 2020. Vitis Unified Software Development Platform 2020 .1 Documentation . https:\/\/www.xilinx.com\/html_docs\/xilinx2020_1\/vitis_doc\/introductionvitishls.html Xilinx. 2020. Vitis Unified Software Development Platform 2020.1 Documentation. https:\/\/www.xilinx.com\/html_docs\/xilinx2020_1\/vitis_doc\/introductionvitishls.html"}],"event":{"name":"PLDI '21: 42nd ACM SIGPLAN International Conference on Programming Language Design and Implementation","location":"Virtual Canada","acronym":"PLDI '21","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages"]},"container-title":["Proceedings of the 42nd ACM SIGPLAN International Conference on Programming Language Design and Implementation"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3453483.3454075","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3453483.3454075","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:47:47Z","timestamp":1750193267000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3453483.3454075"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6,18]]},"references-count":49,"alternative-id":["10.1145\/3453483.3454075","10.1145\/3453483"],"URL":"https:\/\/doi.org\/10.1145\/3453483.3454075","relation":{},"subject":[],"published":{"date-parts":[[2021,6,18]]},"assertion":[{"value":"2021-06-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}