{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T17:51:16Z","timestamp":1775065876741,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,6,22]],"date-time":"2021-06-22T00:00:00Z","timestamp":1624320000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,6,22]]},"DOI":"10.1145\/3453688.3461510","type":"proceedings-article","created":{"date-parts":[[2021,6,18]],"date-time":"2021-06-18T23:13:45Z","timestamp":1624058025000},"page":"71-76","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":34,"title":["Eliminating Iterations of Iterative Methods"],"prefix":"10.1145","author":[{"given":"Tao","family":"Song","sequence":"first","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences &amp; University of Chinese Academy of Sciences, beijing, China"}]},{"given":"Xiaoming","family":"Chen","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences &amp; University of Chinese Academy of Sciences, beijing, China"}]},{"given":"Yinhe","family":"Han","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences &amp; University of Chinese Academy of Sciences, beijing, China"}]}],"member":"320","published-online":{"date-parts":[[2021,6,22]]},"reference":[{"key":"e_1_3_2_3_1_1","doi-asserted-by":"crossref","unstructured":"H. Chang et al. 2011. Physical mechanism of HfO2-based bipolar resistive random access memory. In VLSI-TSA. 1--2.","DOI":"10.1109\/VTSA.2011.5872253"},{"key":"e_1_3_2_3_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2824304"},{"key":"e_1_3_2_3_3_1","volume-title":"PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. In ISCA. 27--39.","author":"Chi P.","year":"2016","unstructured":"P. Chi et al. 2016. PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. In ISCA. 27--39."},{"key":"e_1_3_2_3_4_1","unstructured":"Tim Davis. [n.d.]. SuiteSparse Matrix Collection. https:\/\/sparse.tamu.edu\/"},{"key":"e_1_3_2_3_5_1","volume-title":"Direct Methods for Sparse Linear Systems","unstructured":"Timothy Davis. 2006. Direct Methods for Sparse Linear Systems. Society for Industrial and Applied Mathematics."},{"key":"e_1_3_2_3_6_1","doi-asserted-by":"crossref","unstructured":"B. Feinberg et al. 2018. Enabling Scientific Computing on Memristive Accelerators. In ISCA. 367--382.","DOI":"10.1109\/ISCA.2018.00039"},{"key":"e_1_3_2_3_7_1","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0054-8"},{"key":"e_1_3_2_3_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2445741"},{"key":"e_1_3_2_3_9_1","unstructured":"Maxim Integrated Products Inc. [n.d.]. MAX5214\/MAX5216: 14-\/16-Bit Low-Power Buffered Output Rail-to-Rail DACs with SPI Interface. https:\/\/datasheets.maximintegrated.com\/en\/ds\/MAX5214-MAX5216.pdf"},{"key":"e_1_3_2_3_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"},{"key":"e_1_3_2_3_11_1","unstructured":"Isaac Richter et al. 2015. Memristive Accelerator for Extreme Scale Linear Solvers. Technical Report. University of Rochester. http:\/\/www2.ece.rochester.edu\/~xiguo\/gomac15.pdf"},{"key":"e_1_3_2_3_12_1","volume-title":"Iterative Methods for Sparse Linear Systems. PWS Pub","author":"Saad Y.","unstructured":"Y. Saad. 1996. Iterative Methods for Sparse Linear Systems. PWS Pub. Co."},{"key":"e_1_3_2_3_13_1","volume-title":"ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. In ISCA. 14--26.","author":"Shafiee A.","year":"2016","unstructured":"A. Shafiee et al. 2016. ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. In ISCA. 14--26."},{"key":"e_1_3_2_3_14_1","unstructured":"S. Sheu et al. 2009. A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme. In VLSIC. 82--83."},{"key":"e_1_3_2_3_15_1","doi-asserted-by":"crossref","unstructured":"Z. Sun et al. 2019. Fast Solution of Linear Systems with Analog Resistive Switching Memory (RRAM). In ICRC. 1--5.","DOI":"10.1109\/ICRC.2019.8914709"},{"key":"e_1_3_2_3_16_1","doi-asserted-by":"publisher","DOI":"10.1073\/pnas.1815682116"},{"key":"e_1_3_2_3_17_1","volume-title":"IEEE JSSC","volume":"45","author":"van Elzakker M.","year":"2010","unstructured":"M. van Elzakker et al. 2010. A 10-bit Charge-Redistribution ADC Consuming 1.9\u03bcW at 1 MS\/s. IEEE JSSC, Vol. 45, 5 (May 2010), 1007--1015."},{"key":"e_1_3_2_3_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"e_1_3_2_3_19_1","doi-asserted-by":"crossref","unstructured":"Peng Yao et al. 2017. Face classification using electronic synapses. Nature Communications volume Vol. 8 (2017).","DOI":"10.1038\/ncomms15199"},{"key":"e_1_3_2_3_20_1","volume-title":"Resistive Random Access Memory (RRAM): From Devices to Array Architectures","author":"Yu S.","unstructured":"S. Yu. 2016. Resistive Random Access Memory (RRAM): From Devices to Array Architectures. San Rafael, California."},{"key":"e_1_3_2_3_21_1","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0100-6"}],"event":{"name":"GLSVLSI '21: Great Lakes Symposium on VLSI 2021","location":"Virtual Event USA","acronym":"GLSVLSI '21","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2021 Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3453688.3461510","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3453688.3461510","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:28:46Z","timestamp":1750195726000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3453688.3461510"}},"subtitle":["Solving Large-Scale Sparse Linear System in\n            <i>O<\/i>\n            (1) with RRAM-based In-Memory Accelerator"],"short-title":[],"issued":{"date-parts":[[2021,6,22]]},"references-count":21,"alternative-id":["10.1145\/3453688.3461510","10.1145\/3453688"],"URL":"https:\/\/doi.org\/10.1145\/3453688.3461510","relation":{},"subject":[],"published":{"date-parts":[[2021,6,22]]},"assertion":[{"value":"2021-06-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}