{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:22:51Z","timestamp":1750220571903,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":27,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,6,22]],"date-time":"2021-06-22T00:00:00Z","timestamp":1624320000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,6,22]]},"DOI":"10.1145\/3453688.3461528","type":"proceedings-article","created":{"date-parts":[[2021,6,18]],"date-time":"2021-06-18T23:13:29Z","timestamp":1624058009000},"page":"347-352","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Energy-Efficient Hybrid-RAM with Hybrid Bit-Serial based VMM Support"],"prefix":"10.1145","author":[{"given":"Chen","family":"Nie","sequence":"first","affiliation":[{"name":"Shanghai Jiao Tong University, Shanghai, China"}]},{"given":"Jie","family":"Lin","sequence":"additional","affiliation":[{"name":"University of Central Florida, Orlando, FL, USA"}]},{"given":"Huan","family":"Hu","sequence":"additional","affiliation":[{"name":"Washington State University, Pullmam, WA, USA"}]},{"given":"Li","family":"Jiang","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, Shanghai, China"}]},{"given":"Xiaoyao","family":"Liang","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, Shanghai, China"}]},{"given":"Zhezhi","family":"He","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, Shanghai, China"}]}],"member":"320","published-online":{"date-parts":[[2021,6,22]]},"reference":[{"key":"e_1_3_2_3_1_1","volume-title":"Deep learning","author":"Ian Goodfellow","year":"2016","unstructured":"Ian Goodfellow et al. Deep learning. MIT press Cambridge, 2016."},{"key":"e_1_3_2_3_2_1","volume-title":"Proceedings of the IEEE conference on computer vision and pattern recognition","author":"Kaiming","year":"2016","unstructured":"Kaiming He et al. Deep residual learning for image recognition. In Proceedings of the IEEE conference on computer vision and pattern recognition, 2016."},{"key":"e_1_3_2_3_3_1","first-page":"1731","volume-title":"Energy Policy","author":"K","year":"2007","unstructured":"K Ermis et al. Artificial neural network analysis of world green energy use. Energy Policy, pages 1731--1743, 2007."},{"key":"e_1_3_2_3_4_1","volume-title":"An analysis of deep neural network models for practical applications. arXiv preprint arXiv:1605.07678","author":"Alfredo Canziani","year":"2016","unstructured":"Alfredo Canziani et al. An analysis of deep neural network models for practical applications. arXiv preprint arXiv:1605.07678, 2016."},{"key":"e_1_3_2_3_5_1","first-page":"20","volume-title":"Hitting the memory wall: implications of the obvious. ACM SIGARCH computer architecture news","author":"Wulf Wm A","year":"1995","unstructured":"Wm A Wulf et al. Hitting the memory wall: implications of the obvious. ACM SIGARCH computer architecture news, pages 20--24, 1995."},{"key":"e_1_3_2_3_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757323"},{"key":"e_1_3_2_3_7_1","first-page":"1","volume-title":"Proceedings of the 44th annual international symposium on computer architecture","author":"Norman","year":"2017","unstructured":"Norman P Jouppi et al. In-datacenter performance analysis of a tensor processing unit. In Proceedings of the 44th annual international symposium on computer architecture, pages 1--12, 2017."},{"key":"e_1_3_2_3_8_1","article-title":"A multi-functional in-memory inference processor using a standard 6t sram array","author":"Mingu Kang","year":"2018","unstructured":"Mingu Kang et al. A multi-functional in-memory inference processor using a standard 6t sram array. IEEE Journal of Solid-State Circuits, 2018.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"e_1_3_2_3_9_1","article-title":"In-memory computation of a machine-learning classifier in a standard 6t sram array","author":"Jintao Zhang","year":"2017","unstructured":"Jintao Zhang et al. In-memory computation of a machine-learning classifier in a standard 6t sram array. IEEE Journal of Solid-State Circuits, 2017.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"e_1_3_2_3_10_1","article-title":"A programmable heterogeneous microprocessor based on bit-scalable in-memory computing","author":"Hongyang Jia","year":"2020","unstructured":"Hongyang Jia et al. A programmable heterogeneous microprocessor based on bit-scalable in-memory computing. IEEE Journal of Solid-State Circuits, 2020.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"e_1_3_2_3_11_1","volume-title":"IEEE JSSC","author":"Zhewei","year":"2020","unstructured":"Zhewei Jiang et al. C3sram: An in-memory-computing sram macro based on robust capacitive coupling computing mechanism. IEEE JSSC, 2020."},{"key":"e_1_3_2_3_12_1","article-title":"Conv-sram: An energy-efficient sram with in-memory dot-product computation for low-power convolutional neural networks","author":"Avishek Biswas","year":"2018","unstructured":"Avishek Biswas et al. Conv-sram: An energy-efficient sram with in-memory dot-product computation for low-power convolutional neural networks. IEEE Journal of Solid-State Circuits, 2018.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"e_1_3_2_3_13_1","first-page":"383","volume-title":"2018 ACM\/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)","author":"Charles","year":"2018","unstructured":"Charles Eckert et al. Neural cache: Bit-serial in-cache acceleration of deep neural networks. In 2018 ACM\/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), pages 383--396. IEEE, 2018."},{"key":"e_1_3_2_3_14_1","article-title":"A 28-nm compute sram with bit-serial logic\/arithmetic operations for programmable in-memory vector computing","author":"Jingcheng Wang","year":"2019","unstructured":"Jingcheng Wang et al. A 28-nm compute sram with bit-serial logic\/arithmetic operations for programmable in-memory vector computing. IEEE Journal of Solid-State Circuits, pages 76--86, 2019.","journal-title":"IEEE Journal of Solid-State Circuits, pages 76--86"},{"key":"e_1_3_2_3_15_1","first-page":"1","volume-title":"Design Automation Conference","author":"Kyeongho","year":"2020","unstructured":"Kyeongho Lee et al. Bit parallel 6t sram in-memory computing with reconfigurable bit-precision. In Design Automation Conference, pages 1--6. IEEE, 2020."},{"key":"e_1_3_2_3_16_1","first-page":"273","volume-title":"2017 50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"Vivek","year":"2017","unstructured":"Vivek Seshadri et al. Ambit: In-memory accelerator for bulk bitwise operations using commodity dram technology. In 2017 50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), pages 273--287. IEEE, 2017."},{"key":"e_1_3_2_3_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"e_1_3_2_3_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"e_1_3_2_3_19_1","first-page":"1","volume-title":"Proceedings of the 53rd Annual Design Automation Conference","author":"Shuangchen","year":"2016","unstructured":"Shuangchen Li et al. Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories. In Proceedings of the 53rd Annual Design Automation Conference, pages 1--6, 2016."},{"issue":"05","key":"e_1_3_2_3_20_1","first-page":"377","article-title":"Bit-serial parallel processing systems","volume":"31","author":"Batcher Kenneth E.","year":"1982","unstructured":"Kenneth E. Batcher. Bit-serial parallel processing systems. IEEE Computer Architecture Letters, 31(05):377--384, 1982.","journal-title":"IEEE Computer Architecture Letters"},{"key":"e_1_3_2_3_21_1","volume-title":"VLSI signal processing","author":"Denyer Peter B","year":"1985","unstructured":"Peter B Denyer et al. VLSI signal processing; a bit-serial approach. Addison-Wesley Longman Publishing Co., Inc., 1985."},{"key":"e_1_3_2_3_22_1","first-page":"1","volume-title":"Proceedings of the 56th Annual Design Automation Conference 2019","author":"Zhezhi","year":"2019","unstructured":"Zhezhi He et al. Noise injection adaption: End-to-end reram crossbar non-ideal effect adaption for neural network mapping. In Proceedings of the 56th Annual Design Automation Conference 2019, pages 1--6, 2019."},{"key":"e_1_3_2_3_23_1","first-page":"381","volume-title":"Proceedings of the 2019 on Great Lakes Symposium on VLSI","author":"Bing","year":"2019","unstructured":"Bing Li et al. An overview of in-memory processing with emerging non-volatile memory for data-intensive applications. In Proceedings of the 2019 on Great Lakes Symposium on VLSI, pages 381--386, 2019."},{"key":"e_1_3_2_3_24_1","volume-title":"ESSCIRC 2017--43rd IEEE European Solid State Circuits Conference. IEEE","author":"Singh Harijot","year":"2017","unstructured":"Harijot Singh Bindra et al. A 30fj\/comparison dynamic bias comparator. In ESSCIRC 2017--43rd IEEE European Solid State Circuits Conference. IEEE, 2017."},{"key":"e_1_3_2_3_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"e_1_3_2_3_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2015.7298594"},{"key":"e_1_3_2_3_27_1","volume-title":"et al. Mobilenets: Efficient convolutional neural networks for mobile vision applications. arXiv:1704.04861","author":"Howard Andrew G","year":"2017","unstructured":"Andrew G Howard, Menglong Zhu, et al. Mobilenets: Efficient convolutional neural networks for mobile vision applications. arXiv:1704.04861, 2017."}],"event":{"name":"GLSVLSI '21: Great Lakes Symposium on VLSI 2021","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Virtual Event USA","acronym":"GLSVLSI '21"},"container-title":["Proceedings of the 2021 Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3453688.3461528","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3453688.3461528","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:28:47Z","timestamp":1750195727000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3453688.3461528"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6,22]]},"references-count":27,"alternative-id":["10.1145\/3453688.3461528","10.1145\/3453688"],"URL":"https:\/\/doi.org\/10.1145\/3453688.3461528","relation":{},"subject":[],"published":{"date-parts":[[2021,6,22]]},"assertion":[{"value":"2021-06-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}