{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:42:03Z","timestamp":1773247323684,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":53,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,6,22]],"date-time":"2021-06-22T00:00:00Z","timestamp":1624320000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,6,22]]},"DOI":"10.1145\/3453688.3461760","type":"proceedings-article","created":{"date-parts":[[2021,6,18]],"date-time":"2021-06-18T23:13:45Z","timestamp":1624058025000},"page":"221-228","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":42,"title":["RANE"],"prefix":"10.1145","author":[{"given":"Shervin","family":"Roshanisefat","sequence":"first","affiliation":[{"name":"George Mason University, Fairfax, VA, USA"}]},{"given":"Hadi","family":"Mardani Kamali","sequence":"additional","affiliation":[{"name":"George Mason University, Fairfax, VA, USA"}]},{"given":"Houman","family":"Homayoun","sequence":"additional","affiliation":[{"name":"University of California, Davis, Davis, CA, USA"}]},{"given":"Avesta","family":"Sasan","sequence":"additional","affiliation":[{"name":"George Mason University, Fairfax, VA, USA"}]}],"member":"320","published-online":{"date-parts":[[2021,6,22]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"A. Elzeftawi et al. 2021. Running Cadence JasperGold formal verification on AWS at scale . https:\/\/aws.amazon.com\/blogs\/industries\/tag\/cadence-jaspergold\/."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2459976.2459985"},{"key":"e_1_3_2_1_3_1","volume-title":"Trends in the Global IC Design Service Market . DIGITIMES","author":"Yeh A.","year":"2012","unstructured":"A. Yeh. 2012. Trends in the Global IC Design Service Market . DIGITIMES (2012)."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","unstructured":"B. Shakya et al. 2020. CAS-lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme . IACR Trans. on Cryptographic Hardware and Embedded Systems (CHES) (2020) 175--202.","DOI":"10.46586\/tches.v2020.i1.175-202"},{"key":"e_1_3_2_1_5_1","volume-title":"Proc. of Austrian Workshop on Microelectronics (Austrochip) .","author":"Wolf C.","year":"2013","unstructured":"C. Wolf et al. 2013. Yosys-a free Verilog synthesis suite. In Proc. of Austrian Workshop on Microelectronics (Austrochip) ."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"crossref","unstructured":"D. Sirone and P. Subramanayan. 2020. Functional analysis attacks on logic locking . IEEE TIFS (2020).","DOI":"10.23919\/DATE.2019.8715163"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"F. Koushanfar. 2017. Active Hardware Metering by Finite State Machine Obfuscation . In Hardware Protection through Obfuscation. 161--187.","DOI":"10.1007\/978-3-319-49019-9_7"},{"key":"e_1_3_2_1_8_1","unstructured":"GATE Lab. 2021. RANE framework v.1.0.0 . https:\/\/github.com\/gate-lab\/RANE https:\/\/cadforassurance.org\/tools\/evaluation-of-obfuscation\/rane ."},{"key":"e_1_3_2_1_9_1","unstructured":"GMU Office of Research Computing. 2021. ARGO Cluster . http:\/\/wiki.orc.gmu.edu\/mediawiki ."},{"key":"e_1_3_2_1_10_1","volume-title":"LUT-lock: A Novel LUT-based Logic Obfuscation for FPGA-bitstream and ASIC-hardware Protection. In IEEE Annual Symp. on VLSI (ISVLSI) . 405--410","author":"Kamali H. M.","year":"2018","unstructured":"H. M. Kamali et al. 2018. LUT-lock: A Novel LUT-based Logic Obfuscation for FPGA-bitstream and ASIC-hardware Protection. In IEEE Annual Symp. on VLSI (ISVLSI) . 405--410."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317831"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"H. M. Kamali et al. 2020 a. InterLock: An Intercorrelated Logic and Routing Locking. In Int'l Conf. On Computer Aided Design (ICCAD). 1--9.","DOI":"10.1145\/3400302.3415667"},{"key":"e_1_3_2_1_13_1","volume-title":"On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic. In Great Lakes Symp. on VLSI (GLSVLSI). 217--222","author":"Kamali H. M.","year":"2020","unstructured":"H. M. Kamali et al. 2020 b. On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic. In Great Lakes Symp. on VLSI (GLSVLSI). 217--222."},{"key":"e_1_3_2_1_14_1","volume-title":"Connectivity and Routing Augmentation Model for Building Logic Encryption. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 153--159","author":"Kamali H. M.","year":"2020","unstructured":"H. M. Kamali et al. 2020 c. SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 153--159."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"H. Zhou et al. 2017. CycSAT: SAT-based Attack on Cyclic Logic Encryptions. In ICCAD. 49--56.","DOI":"10.1109\/ICCAD.2017.8203759"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2697960"},{"key":"e_1_3_2_1_17_1","volume-title":"Security Analysis of Logic Obfuscation. In Design Automation Conf. (DAC) . 83--89","author":"Rajendran J.","year":"2012","unstructured":"J. Rajendran et al. 2012. Security Analysis of Logic Obfuscation. In Design Automation Conf. (DAC) . 83--89."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403631"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"crossref","unstructured":"J. Sweeney et al. 2020. Latch-Based Logic Locking. In Int'l Symp. on Hardware Oriented Security and Trust (HOST). 132--141.","DOI":"10.1109\/HOST45689.2020.9300256"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"crossref","unstructured":"K. Shamsi et al. 2017a. AppSAT: Approximately Deobfuscating Integrated Circuits. In HOST. 95--100.","DOI":"10.1109\/HST.2017.7951805"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"crossref","unstructured":"K. Shamsi et al. 2017b. Cyclic Obfuscation for Creating SAT-Unresolvable Circuits. In GLSVLSI . 173--178.","DOI":"10.1145\/3060403.3060458"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715053"},{"key":"e_1_3_2_1_23_1","unstructured":"K. Z. Azar et al. 2019 a. COMA: Communication and Obfuscation Management Architecture. In Int'l Symp. on Research in Attacks Intrusions and Defenses (RAID). 181--195."},{"key":"e_1_3_2_1_24_1","volume-title":"2019 b. SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks . IACR Trans. on Cryptographic Hardware and Embedded Systems (CHES)","author":"Azar K. Z.","year":"2019","unstructured":"K. Z. Azar et al. 2019 b. SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks . IACR Trans. on Cryptographic Hardware and Embedded Systems (CHES) (2019), 97--122."},{"key":"e_1_3_2_1_25_1","volume-title":"Threats on Logic Locking: A Decade Later. In Great Lakes Symp. on VLSI (GLSVLSI) . 471--476","author":"Azar K. Z.","year":"2019","unstructured":"K. Z. Azar et al. 2019 c. Threats on Logic Locking: A Decade Later. In Great Lakes Symp. on VLSI (GLSVLSI) . 471--476."},{"key":"e_1_3_2_1_26_1","first-page":"4","article-title":"2021. Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits","volume":"29","author":"Azar K. Z.","year":"2021","unstructured":"K. Z. Azar et al. 2021. Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits . IEEE Trans. on Very Large Scale Integration (VLSI) Systems , Vol. 29, 4 (2021), 643--656.","journal-title":"IEEE Trans. on Very Large Scale Integration (VLSI) Systems"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415669"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"crossref","unstructured":"L. Alrahis et al. 2019. ScanSAT: Unlocking Obfuscated Scan Chains. In ASP-DAC. 352--357.","DOI":"10.1145\/3287624.3287693"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"crossref","unstructured":"L. De Moura. 2014. Yices 2.2. In Int'l Conf. on Computer Aided Verification. 737--744.","DOI":"10.1007\/978-3-319-08867-9_49"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"crossref","unstructured":"L. De Moura et al. 2008. Z3: An Efficient SMT Solver. In Int'l Conf. on Tools and Algorithms for the Construction and Analysis of Systems. 337--340.","DOI":"10.1007\/978-3-540-78800-3_24"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"crossref","unstructured":"M. El Massad et al. 2015. Integrated Circuit (IC) Decamouflaging: Reverse Engineering Camouflaged ICs within Minutes. In NDSS .","DOI":"10.14722\/ndss.2015.23218"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"crossref","unstructured":"M. El Massad et al. 2017. Reverse Engineering Camouflaged Sequential Circuits without Scan Access. In Int'l Conf. On Computer Aided Design (ICCAD). 33--40.","DOI":"10.1109\/ICCAD.2017.8203757"},{"key":"e_1_3_2_1_33_1","volume-title":"PySMT: A Solver-agnostic Library for Fast Prototyping of SMT-based Algorithms. In SMT workshop .","author":"Gario M.","year":"2015","unstructured":"M. Gario et al. . 2015. PySMT: A Solver-agnostic Library for Fast Prototyping of SMT-based Algorithms. In SMT workshop ."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2335155"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"crossref","unstructured":"M. Yasin et al. 2016. SARLock: SAT Attack Resistant Logic Locking. In HOST. 236--241.","DOI":"10.1109\/HST.2016.7495588"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3133985"},{"key":"e_1_3_2_1_37_1","volume-title":"Automation & Test in Europe Conf. & Exhibition (DATE). 270--273","author":"Limaye N.","unstructured":"N. Limaye and O. Sinanoglu. 2020. DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic Keys. In Design, Automation & Test in Europe Conf. & Exhibition (DATE). 270--273."},{"key":"e_1_3_2_1_38_1","article-title":"2020. Thwarting All Logic Locking Attacks: Dishonest Oracle with Truly Random Logic Locking","author":"Limaye N.","year":"2020","unstructured":"N. Limaye et al. . 2020. Thwarting All Logic Locking Attacks: Dishonest Oracle with Truly Random Logic Locking . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2020).","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ("},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"crossref","unstructured":"N. Limaye et al. 2019. Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan. In ICCAD. 1--8.","DOI":"10.1109\/ICCAD45719.2019.8942047"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"crossref","unstructured":"P. Subramanyan et al. 2015. Evaluating the Security of Logic Encryption Algorithms. In Int'l Symp. on Hardware Oriented Security and Trust (HOST). 137--143.","DOI":"10.1109\/HST.2015.7140252"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"crossref","unstructured":"P. Tuyls et al. 2006. Read-Proof Hardware from Protective Coatings. In Int'l Workshop on Cryptographic Hardware and Embedded Systems (CHES). 369--383.","DOI":"10.1007\/11894063_29"},{"key":"e_1_3_2_1_42_1","volume-title":"ABC: An Academic Industrial-strength Verification Tool. In Int'l Conf. on Computer Aided Verification. 24--40.","author":"Brayton R.","year":"2010","unstructured":"R. Brayton et al. 2010. ABC: An Academic Industrial-strength Verification Tool. In Int'l Conf. on Computer Aided Verification. 24--40."},{"key":"e_1_3_2_1_43_1","volume-title":"Boolector: An efficient SMT solver for bit-vectors and arrays. In Int'l Conf. on Tools and Algorithms for the Construction and Analysis of Systems . 174--177.","author":"Brummayer R.","year":"2009","unstructured":"R. Brummayer et al. 2009. Boolector: An efficient SMT solver for bit-vectors and arrays. In Int'l Conf. on Tools and Algorithms for the Construction and Analysis of Systems . 174--177."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2028166"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"crossref","unstructured":"S. Roshanisefat et al. 2018a. Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes. In IEEE Int'l Symp. on On-Line Testing And Robust System Design (IOLTS). 275--280.","DOI":"10.1109\/IOLTS.2018.8474189"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/3194554.3194596"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS48691.2020.9107629"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.2968552"},{"key":"e_1_3_2_1_49_1","volume-title":"Pyverilog: A Python-based Hardware Design Processing Toolkit for Verilog HDL. In Int'l Symp. on Applied Reconfigurable Computing. 451--460.","author":"Takamaeda-Yamazaki S.","year":"2015","unstructured":"S. Takamaeda-Yamazaki. 2015. Pyverilog: A Python-based Hardware Design Processing Toolkit for Verilog HDL. In Int'l Symp. on Applied Reconfigurable Computing. 451--460."},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3288739"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2797019"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"crossref","unstructured":"X. Xu et al. 2017. Novel Bypass Attack and BDD-based Trade-off against all Known Logic Locking Attacks. In CHES. 189--210.","DOI":"10.1007\/978-3-319-66787-4_10"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"crossref","unstructured":"Y. Xie and A. Srivastava. 2016. Mitigating SAT Attack on Logic Locking. In CHES. 127--146.","DOI":"10.1007\/978-3-662-53140-2_7"}],"event":{"name":"GLSVLSI '21: Great Lakes Symposium on VLSI 2021","location":"Virtual Event USA","acronym":"GLSVLSI '21","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2021 Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3453688.3461760","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3453688.3461760","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:28:47Z","timestamp":1750195727000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3453688.3461760"}},"subtitle":["An Open-Source Formal De-obfuscation Attack for Reverse Engineering of Logic Encrypted Circuits"],"short-title":[],"issued":{"date-parts":[[2021,6,22]]},"references-count":53,"alternative-id":["10.1145\/3453688.3461760","10.1145\/3453688"],"URL":"https:\/\/doi.org\/10.1145\/3453688.3461760","relation":{},"subject":[],"published":{"date-parts":[[2021,6,22]]},"assertion":[{"value":"2021-06-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}