{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:19:17Z","timestamp":1750220357233,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":23,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,5,11]],"date-time":"2021-05-11T00:00:00Z","timestamp":1620691200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,5,11]]},"DOI":"10.1145\/3457388.3458660","type":"proceedings-article","created":{"date-parts":[[2021,4,29]],"date-time":"2021-04-29T22:15:17Z","timestamp":1619734517000},"page":"21-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Dynamic row activation mechanism for multi-core systems"],"prefix":"10.1145","author":[{"given":"Tareq","family":"Alawneh","sequence":"first","affiliation":[{"name":"University of Hertfordshire, Hatfield, United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Raimund","family":"Kirner","sequence":"additional","affiliation":[{"name":"University of Hertfordshire, Hatfield, United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Catherine","family":"Menon","sequence":"additional","affiliation":[{"name":"University of Hertfordshire, Hatfield, United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2021,5,11]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/EMPDP.2019.8671566"},{"volume-title":"Proceedings of the 28th IEEE International Conference on Microelectronics, ICM. 125--128","author":"Alawneh T.","key":"e_1_3_2_1_2_1","unstructured":"T. Alawneh and A. Elhossini . 2016. A Data Access Prediction Unit for Multi-media Applications . In Proceedings of the 28th IEEE International Conference on Microelectronics, ICM. 125--128 . T. Alawneh and A. Elhossini. 2016. A Data Access Prediction Unit for Multi-media Applications. In Proceedings of the 28th IEEE International Conference on Microelectronics, ICM. 125--128."},{"volume-title":"Proceedings of the 15th ACM International Conference on Computing Frontiers, CF. 78--87","author":"Alawneh T.","key":"e_1_3_2_1_3_1","unstructured":"T. Alawneh and A. Elhossini . 2018. A Prefetch-Aware Memory System for Data Access Patterns in Multimedia Applications . In Proceedings of the 15th ACM International Conference on Computing Frontiers, CF. 78--87 . T. Alawneh and A. Elhossini. 2018. A Prefetch-Aware Memory System for Data Access Patterns in Multimedia Applications. In Proceedings of the 15th ACM International Conference on Computing Frontiers, CF. 78--87."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","unstructured":"E. C. Balis and B. Jacob. 2010. Fine-Grained Activation for Power Reduction in DRAM. IEEE Micro 30 (April 2010) 34--47.  E. C. Balis and B. Jacob. 2010. Fine-Grained Activation for Power Reduction in DRAM. IEEE Micro 30 (April 2010) 34--47.","DOI":"10.1109\/MM.2010.43"},{"volume-title":"Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, PACT. 72--81","author":"Bienia C.","key":"e_1_3_2_1_5_1","unstructured":"C. Bienia , S. Kumar , J. P. Singh , and K. Li . 2008. The PARSEC Benchmark Suite: Characterization and Architectural Implications . In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, PACT. 72--81 . C. Bienia, S. Kumar, J. P. Singh, and K. Li. 2008. The PARSEC Benchmark Suite: Characterization and Architectural Implications. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, PACT. 72--81."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"crossref","unstructured":"N. Binkert B. Beckmann G. Black S. K. Reinhardt A. Saidi A. Basu J. Hestness D. R. Hower T. Krishna S. Sardashti R. Sen K. Sewell M. Shoaib N. Vaish M. D. Hill and D. A. Wood. 2011. The Gem5 Simulator. ACM SIGARCH Computer Architecture News 39 (May 2011) 1--7.  N. Binkert B. Beckmann G. Black S. K. Reinhardt A. Saidi A. Basu J. Hestness D. R. Hower T. Krishna S. Sardashti R. Sen K. Sewell M. Shoaib N. Vaish M. D. Hill and D. A. Wood. 2011. The Gem5 Simulator. ACM SIGARCH Computer Architecture News 39 (May 2011) 1--7.","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_7_1","volume":"201","author":"Chatterjee N.","unstructured":"N. Chatterjee , M. O'Connor , D. Lee , D. R. Johnson , S. W. Keckler , M. Rhu , and W. J. Dally. 201 7. Architecting an Energy-Efficient DRAM System for GPUs. In Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, HPCA. 73--84. N. Chatterjee, M. O'Connor, D. Lee, D. R. Johnson, S. W. Keckler, M. Rhu, and W. J. Dally. 2017. Architecting an Energy-Efficient DRAM System for GPUs. In Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, HPCA. 73--84.","journal-title":"J. Dally."},{"volume-title":"Proceedings of the 2nd International Symposium on Memory Systems, MEMSYS. 311--321","author":"Ghasempour M.","key":"e_1_3_2_1_8_1","unstructured":"M. Ghasempour , A. Jaleel , J. D. Garside , and M. Luj\u00e1n . 2016. HAPPY: Hybrid Address-based Page Policy in DRAMs . In Proceedings of the 2nd International Symposium on Memory Systems, MEMSYS. 311--321 . M. Ghasempour, A. Jaleel, J. D. Garside, and M. Luj\u00e1n. 2016. HAPPY: Hybrid Address-based Page Policy in DRAMs. In Proceedings of the 2nd International Symposium on Memory Systems, MEMSYS. 311--321."},{"volume-title":"Proceedings of the 26th ACM International Conference on Super-computing, ICS. 257--266","author":"Gulur N.","key":"e_1_3_2_1_9_1","unstructured":"N. Gulur , R. Manikantan , M. Mehendale , and R. Govindarajan . 2012. Multiple Sub-Row Buffers in DRAM: Unlocking Performance and Energy Improvement Opportunities . In Proceedings of the 26th ACM International Conference on Super-computing, ICS. 257--266 . N. Gulur, R. Manikantan, M. Mehendale, and R. Govindarajan. 2012. Multiple Sub-Row Buffers in DRAM: Unlocking Performance and Energy Improvement Opportunities. In Proceedings of the 26th ACM International Conference on Super-computing, ICS. 257--266."},{"volume-title":"Proceedings of the 49th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO. 1--12","author":"Ha H.","key":"e_1_3_2_1_10_1","unstructured":"H. Ha , A. Pedram , S. Richardson , S. Kvatinsky , and M. Horowitz . 2016. Improving Energy Efficiency of DRAM by Exploiting Half Page Row Access . In Proceedings of the 49th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO. 1--12 . H. Ha, A. Pedram, S. Richardson, S. Kvatinsky, and M. Horowitz. 2016. Improving Energy Efficiency of DRAM by Exploiting Half Page Row Access. In Proceedings of the 49th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO. 1--12."},{"volume-title":"Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO. 24--35","author":"Kaseridis D.","key":"e_1_3_2_1_11_1","unstructured":"D. Kaseridis , J. Stuecheli , and L. K. John . 2011. Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era . In Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO. 24--35 . D. Kaseridis, J. Stuecheli, and L. K. John. 2011. Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era. In Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO. 24--35."},{"volume-title":"Proceedings of the 39th Annual International Symposium on Computer Architecture, ISCA. 368--379","author":"Kim Y.","key":"e_1_3_2_1_12_1","unstructured":"Y. Kim , V. Seshadri , D. Lee , J. Liu , and O. Mutlu . 2012. A case for exploiting subarray-level parallelism (SALP) in DRAM . In Proceedings of the 39th Annual International Symposium on Computer Architecture, ISCA. 368--379 . Y. Kim, V. Seshadri, D. Lee, J. Liu, and O. Mutlu. 2012. A case for exploiting subarray-level parallelism (SALP) in DRAM. In Proceedings of the 39th Annual International Symposium on Computer Architecture, ISCA. 368--379."},{"volume-title":"Proceedings of the IEEE International Conferenc Solid-State Circuits, ISSCC. 40--41","author":"Koo K.","key":"e_1_3_2_1_13_1","unstructured":"K. Koo , S. Ok , Y. Kang , S. Kim , C. Song , H. Lee , H. Kim , Y. Kim , J. Lee , S. Oak , Y. Lee , J. Lee , J. Lee , H. Lee , J. Jang , J. Jung , B. Choi , Y. Kim , Y. Hur , Y. Kim , B. Chung , and Y. Kim . 2012. A 1.2V 38nm 2.4Gb\/s\/pin 2Gb DDR4 SDRAM with bank group and x4 half-page architecture . In Proceedings of the IEEE International Conferenc Solid-State Circuits, ISSCC. 40--41 . K. Koo, S. Ok, Y. Kang, S. Kim, C. Song, H. Lee, H. Kim, Y. Kim, J. Lee, S. Oak, Y. Lee, J. Lee, J. Lee, H. Lee, J. Jang, J. Jung, B. Choi, Y. Kim, Y. Hur, Y. Kim, B. Chung, and Y. Kim. 2012. A 1.2V 38nm 2.4Gb\/s\/pin 2Gb DDR4 SDRAM with bank group and x4 half-page architecture. In Proceedings of the IEEE International Conferenc Solid-State Circuits, ISSCC. 40--41."},{"volume-title":"Proceedings of the 30th Annual International Symposium on Microarchitecture, MICRO. 330--335","author":"Lee C.","key":"e_1_3_2_1_14_1","unstructured":"C. Lee , M. Potkonjak , and W. H. Mangione-Smith . 1997. Mediabench: a tool for evaluating and synthesizing multimedia and communications systems . In Proceedings of the 30th Annual International Symposium on Microarchitecture, MICRO. 330--335 . C. Lee, M. Potkonjak, and W. H. Mangione-Smith. 1997. Mediabench: a tool for evaluating and synthesizing multimedia and communications systems. In Proceedings of the 30th Annual International Symposium on Microarchitecture, MICRO. 330--335."},{"volume-title":"Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, HPCA. 217--228","author":"Lee Y.","key":"e_1_3_2_1_15_1","unstructured":"Y. Lee , H. Kim , S. Hong , and S. Kim . 2017. Partial Row Activation for Low-Power DRAM System . In Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, HPCA. 217--228 . Y. Lee, H. Kim, S. Hong, and S. Kim. 2017. Partial Row Activation for Low-Power DRAM System. In Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, HPCA. 217--228."},{"key":"e_1_3_2_1_16_1","first-page":"41","volume":"200","unstructured":"Micron Technology Inc. 200 7. TN- 41 - 01 : Calculating Memory System Power For DDR3. Micron Technology Inc. 2007. TN-41-01: Calculating Memory System Power For DDR3.","journal-title":"Micron Technology Inc."},{"key":"e_1_3_2_1_17_1","volume-title":"MT41K512M8DA-107 Data sheet","author":"Micron Technology Inc.","year":"2017","unstructured":"Micron Technology Inc. , MT41K512M8DA-107 Data sheet . 2017 . Micron DDR3 SDRAM Part, 4Gb: x4, x8, x16 DDR3L SDRAM Description . http:\/\/www.micron.com\/products\/dram\/ddr3-sdram. Micron Technology Inc., MT41K512M8DA-107 Data sheet. 2017. Micron DDR3 SDRAM Part, 4Gb: x4, x8, x16 DDR3L SDRAM Description. http:\/\/www.micron.com\/products\/dram\/ddr3-sdram."},{"volume-title":"Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC. 1059--1070","author":"Son Y. H.","key":"e_1_3_2_1_18_1","unstructured":"Y. H. Son , S. O, H. Yang , D. Jung , J. H. Ahn , J. Kim , J. Kim , and J. W. Lee . 2014. Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems . In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC. 1059--1070 . Y. H. Son, S. O, H. Yang, D. Jung, J. H. Ahn, J. Kim, J. Kim, and J. W. Lee. 2014. Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC. 1059--1070."},{"key":"e_1_3_2_1_19_1","unstructured":"S. Thoziyoor N. Muralimanohar J. H. Ahn and N. P. Jouppi. 2008. CACTI 5.1. In Technical Report HPL-2008-20 Hewlett Packard Labs.  S. Thoziyoor N. Muralimanohar J. H. Ahn and N. P. Jouppi. 2008. CACTI 5.1. In Technical Report HPL-2008-20 Hewlett Packard Labs."},{"volume-title":"Proceedings of the 37th Annual International Symposium on Computer Architectureg, ISCA. 175--186","author":"Udipi A. N.","key":"e_1_3_2_1_20_1","unstructured":"A. N. Udipi , N. Muralimanohar , N. Chatterjee , R. Balasubramonian , A. Davis , and N. P. Jouppi . 2010. Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores . In Proceedings of the 37th Annual International Symposium on Computer Architectureg, ISCA. 175--186 . A. N. Udipi, N. Muralimanohar, N. Chatterjee, R. Balasubramonian, A. Davis, and N. P. Jouppi. 2010. Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores. In Proceedings of the 37th Annual International Symposium on Computer Architectureg, ISCA. 175--186."},{"key":"e_1_3_2_1_21_1","unstructured":"Xilinx Inc. 2019. Vivado Design Suite. https:\/\/www.xilinx.com\/support\/download.html.  Xilinx Inc. 2019. Vivado Design Suite. https:\/\/www.xilinx.com\/support\/download.html."},{"volume-title":"Proceedings of the 2017 IEEE\/ACM International Symposium on Low Power Electronics and Design, ISLPED. 1--6.","author":"Zhang C.","key":"e_1_3_2_1_22_1","unstructured":"C. Zhang and X. Guo . 2017. Enabling Efficient Fine-Grained DRAM Activations with Interleaved I\/O . In Proceedings of the 2017 IEEE\/ACM International Symposium on Low Power Electronics and Design, ISLPED. 1--6. C. Zhang and X. Guo. 2017. Enabling Efficient Fine-Grained DRAM Activations with Interleaved I\/O. In Proceedings of the 2017 IEEE\/ACM International Symposium on Low Power Electronics and Design, ISLPED. 1--6."},{"volume-title":"Proceedings of the 2014 ACM\/IEEE 41st International Symposium on Computer Architecture, ISCA. 349--360","author":"Zhang T.","key":"e_1_3_2_1_23_1","unstructured":"T. Zhang , K. Chen , C. Xu , G. Sun , T. Wang , and Y. Xie . 2014. Half-DRAM: a High-bandwidth and Low-power DRAM Architecture from the Rethinking of Fine-grained Activation . In Proceedings of the 2014 ACM\/IEEE 41st International Symposium on Computer Architecture, ISCA. 349--360 . T. Zhang, K. Chen, C. Xu, G. Sun, T. Wang, and Y. Xie. 2014. Half-DRAM: a High-bandwidth and Low-power DRAM Architecture from the Rethinking of Fine-grained Activation. In Proceedings of the 2014 ACM\/IEEE 41st International Symposium on Computer Architecture, ISCA. 349--360."}],"event":{"name":"CF '21: Computing Frontiers Conference","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Virtual Event Italy","acronym":"CF '21"},"container-title":["Proceedings of the 18th ACM International Conference on Computing Frontiers"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3457388.3458660","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3457388.3458660","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:17:20Z","timestamp":1750191440000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3457388.3458660"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,5,11]]},"references-count":23,"alternative-id":["10.1145\/3457388.3458660","10.1145\/3457388"],"URL":"https:\/\/doi.org\/10.1145\/3457388.3458660","relation":{},"subject":[],"published":{"date-parts":[[2021,5,11]]},"assertion":[{"value":"2021-05-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}