{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:46:50Z","timestamp":1750308410202,"version":"3.41.0"},"reference-count":39,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2021,7,17]],"date-time":"2021-07-17T00:00:00Z","timestamp":1626480000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001843","name":"Science and Engineering Research Board","doi-asserted-by":"publisher","award":["EEQ\/2019\/000695"],"award-info":[{"award-number":["EEQ\/2019\/000695"]}],"id":[{"id":"10.13039\/501100001843","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2021,12,31]]},"abstract":"<jats:p>\n            In recent years, DRAM-based main memories have become susceptible to the Row Hammer (RH) problem, which causes bits to flip in a row without accessing them directly. Frequent activation of a row, called an\n            <jats:italic>aggressor row<\/jats:italic>\n            , causes its adjacent rows\u2019 (\n            <jats:italic>victim<\/jats:italic>\n            ) bits to flip. The state-of-the-art solution is to refresh the victim rows explicitly to prevent bit flipping. There have been several proposals made to detect RH attacks. These include both probabilistic as well as deterministic counter-based methods. The technique of handling RH attacks, however, remains the same. In this work, we propose an efficient technique for handling the RH problem. We show that the mechanism is agnostic of the detection mechanism. Our RH handling technique omits the necessity of refreshing the victim rows. Instead, we use a small non-volatile Spin-Transfer Torque Magnetic Random Access Memory (STTRAM) that ensures no unnecessary refreshes of the victim rows on the DRAM device and thus allowing more time for normal applications in the same DRAM device. Our model relies on the migration of the aggressor rows. This accounts for removing blocking of the DRAM operations due to the refreshing of victim rows incurred in the previous solution. After extensive evaluation, we found that, compared to the conventional RH mitigation techniques, our model minimizes the blocking time of the memory that is imposed due to explicit refreshing by an average of 80.72% in the worst-case scenario and provides energy savings of about 15.82% on average, across different types of RH-based workloads. A lookup table is necessary to pinpoint the location of a particular row, which, when combined with the STTMRAM, limits the storage overhead to 0.39% of a 2 GB DRAM. Our proposed model prevents repeated refreshing of the same victim rows in different refreshing windows on the DRAM device and leads to an efficient RH handling technique.\n          <\/jats:p>","DOI":"10.1145\/3458749","type":"journal-article","created":{"date-parts":[[2021,7,17]],"date-time":"2021-07-17T10:05:22Z","timestamp":1626516322000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Towards Enhanced System Efficiency while Mitigating Row Hammer"],"prefix":"10.1145","volume":"18","author":[{"given":"Kaustav","family":"Goswami","sequence":"first","affiliation":[{"name":"Indian Institute of Information Technology Guwahati, India"}]},{"given":"Dip Sankar","family":"Banerjee","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Jodhpur, India"}]},{"given":"Shirshendu","family":"Das","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Ropar, India"}]}],"member":"320","published-online":{"date-parts":[[2021,7,17]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_2_1_1_1","DOI":"10.1145\/3132402.3132416"},{"doi-asserted-by":"publisher","key":"e_1_2_1_2_1","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_2_1_3_1","first-page":"2","article-title":"Emerging NVM: A survey on architectural integration and research challenges","volume":"23","author":"Boukhobza Jalil","year":"2017","unstructured":"Jalil Boukhobza , St\u00e9phane Rubini , Renhai Chen , and Zili Shao . 2017 . Emerging NVM: A survey on architectural integration and research challenges . ACM Trans. Des. Autom. Electron. Syst. 23 , 2 (Nov. 2017). Jalil Boukhobza, St\u00e9phane Rubini, Renhai Chen, and Zili Shao. 2017. Emerging NVM: A survey on architectural integration and research challenges. ACM Trans. Des. Autom. Electron. Syst. 23, 2 (Nov. 2017).","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"volume-title":"Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 61\u201372","author":"Cha S.","unstructured":"S. Cha , O. Seongil , H. Shin , S. Hwang , K. Park , S. J. Jang , J. S. Choi , G. Y. Jin , Y. H. Son , H. Cho , J. H. Ahn , and N. S. Kim . 2017. Defect analysis and cost-effective resilience architecture for future DRAM devices . In Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 61\u201372 . S. Cha, O. Seongil, H. Shin, S. Hwang, K. Park, S. J. Jang, J. S. Choi, G. Y. Jin, Y. H. Son, H. Cho, J. H. Ahn, and N. S. Kim. 2017. Defect analysis and cost-effective resilience architecture for future DRAM devices. In Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 61\u201372.","key":"e_1_2_1_4_1"},{"volume-title":"Proceedings of the 68th Device Research Conference. IEEE, 249\u2013252","author":"Chen E.","unstructured":"E. Chen , D. Lottis , A. Driskill-Smith , D. Druist , V. Nikitin , S. Watts , X. Tang , and D. Apalkov . 2010. Non-volatile spin-transfer torque RAM (STT-RAM) . In Proceedings of the 68th Device Research Conference. IEEE, 249\u2013252 . E. Chen, D. Lottis, A. Driskill-Smith, D. Druist, V. Nikitin, S. Watts, X. Tang, and D. Apalkov. 2010. Non-volatile spin-transfer torque RAM (STT-RAM). In Proceedings of the 68th Device Research Conference. IEEE, 249\u2013252.","key":"e_1_2_1_5_1"},{"volume-title":"Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC\u201916)","author":"Chi P.","unstructured":"P. Chi , S. Li , Yuanqing Cheng , Yu Lu , S. H. Kang , and Y. Xie . 2016. Architecture design with STT-RAM: Opportunities and challenges . In Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC\u201916) . 109\u2013114. P. Chi, S. Li, Yuanqing Cheng, Yu Lu, S. H. Kang, and Y. Xie. 2016. Architecture design with STT-RAM: Opportunities and challenges. In Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC\u201916). 109\u2013114.","key":"e_1_2_1_6_1"},{"volume-title":"Proceedings of the IEEE International Solid-state Circuits Conference. IEEE, 46\u201348","author":"Choi Y.","unstructured":"Y. Choi , I. Song , M. Park , H. Chung , S. Chang , B. Cho , J. Kim , Y. Oh , D. Kwon , J. Sunwoo , J. Shin , Y. Rho , C. Lee , M. G. Kang , J. Lee , Y. Kwon , S. Kim , J. Kim , Y. Lee , Q. Wang , S. Cha , S. Ahn , H. Horii , J. Lee , K. Kim , H. Joo , K. Lee , Y. Lee , J. Yoo , and G. Jeong . 2012. A 20nm 1.8V 8Gb PRAM with 40MB\/s program bandwidth . In Proceedings of the IEEE International Solid-state Circuits Conference. IEEE, 46\u201348 . Y. Choi, I. Song, M. Park, H. Chung, S. Chang, B. Cho, J. Kim, Y. Oh, D. Kwon, J. Sunwoo, J. Shin, Y. Rho, C. Lee, M. G. Kang, J. Lee, Y. Kwon, S. Kim, J. Kim, Y. Lee, Q. Wang, S. Cha, S. Ahn, H. Horii, J. Lee, K. Kim, H. Joo, K. Lee, Y. Lee, J. Yoo, and G. Jeong. 2012. A 20nm 1.8V 8Gb PRAM with 40MB\/s program bandwidth. In Proceedings of the IEEE International Solid-state Circuits Conference. IEEE, 46\u201348.","key":"e_1_2_1_7_1"},{"key":"e_1_2_1_8_1","volume-title":"TRRespass: Exploiting the Many Sides of Target Row Refresh. arxiv:cs.CR\/2004.01807","author":"Frigo Pietro","year":"2020","unstructured":"Pietro Frigo , Emanuele Vannacci , Hasan Hassan , Victor van der Veen , Onur Mutlu , Cristiano Giuffrida , Herbert Bos , and Kaveh Razavi . 2020. TRRespass: Exploiting the Many Sides of Target Row Refresh. arxiv:cs.CR\/2004.01807 ( 2020 ). Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi. 2020. TRRespass: Exploiting the Many Sides of Target Row Refresh. arxiv:cs.CR\/2004.01807 (2020)."},{"doi-asserted-by":"publisher","key":"e_1_2_1_9_1","DOI":"10.1109\/TVLSI.2019.2918385"},{"doi-asserted-by":"publisher","key":"e_1_2_1_10_1","DOI":"10.1145\/3307650.3322231"},{"doi-asserted-by":"publisher","key":"e_1_2_1_11_1","DOI":"10.1145\/2934583.2934614"},{"unstructured":"JEDEC. 2014. Wide I\/O 2 (WideIO2). Technical Report JESD229-2.  JEDEC. 2014. Wide I\/O 2 (WideIO2). Technical Report JESD229-2.","key":"e_1_2_1_12_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_14_1","DOI":"10.1109\/ACCESS.2020.2967217"},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the IEEE 36th International Conference on Computer Design (ICCD\u201918)","author":"Khan M. N. I.","year":"2018","unstructured":"M. N. I. Khan and S. Ghosh . 2018. Analysis of row hammer attack on STTRAM . In Proceedings of the IEEE 36th International Conference on Computer Design (ICCD\u201918) . 75\u201382. DOI:https:\/\/doi.org\/10.1109\/ICCD. 2018 .00021 10.1109\/ICCD.2018.00021 M. N. I. Khan and S. Ghosh. 2018. Analysis of row hammer attack on STTRAM. In Proceedings of the IEEE 36th International Conference on Computer Design (ICCD\u201918). 75\u201382. DOI:https:\/\/doi.org\/10.1109\/ICCD.2018.00021"},{"key":"e_1_2_1_16_1","volume-title":"Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques. arxiv:cs.AR\/2005.13121","author":"Kim Jeremie S.","year":"2020","unstructured":"Jeremie S. Kim , Minesh Patel , A. Giray Yaglikci , Hasan Hassan , Roknoddin Azizi , Lois Orosa , and Onur Mutlu . 2020. Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques. arxiv:cs.AR\/2005.13121 ( 2020 ). Jeremie S. Kim, Minesh Patel, A. Giray Yaglikci, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu. 2020. Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques. arxiv:cs.AR\/2005.13121 (2020)."},{"doi-asserted-by":"publisher","key":"e_1_2_1_17_1","DOI":"10.1109\/TC.2019.2907248"},{"doi-asserted-by":"publisher","key":"e_1_2_1_18_1","DOI":"10.1145\/2678373.2665726"},{"doi-asserted-by":"publisher","key":"e_1_2_1_19_1","DOI":"10.1109\/LCA.2015.2414456"},{"volume-title":"Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE\u201915)","author":"Komalan M. P.","unstructured":"M. P. Komalan , C. Tenllado , J. I. G. P\u00e9rez , F. T. Fern\u00e1ndez , and F. Catthoor . 2015. System level exploration of a STT-MRAM based level 1 data-cache . In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE\u201915) . 1311\u20131316. M. P. Komalan, C. Tenllado, J. I. G. P\u00e9rez, F. T. Fern\u00e1ndez, and F. Catthoor. 2015. System level exploration of a STT-MRAM based level 1 data-cache. In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE\u201915). 1311\u20131316.","key":"e_1_2_1_20_1"},{"doi-asserted-by":"crossref","unstructured":"K. Kondo K. Takahashi and Morihiro Kada. 2015. Three-dimensional Integration of Semiconductors: Processing Materials and Applications.  K. Kondo K. Takahashi and Morihiro Kada. 2015. Three-dimensional Integration of Semiconductors: Processing Materials and Applications.","key":"e_1_2_1_21_1","DOI":"10.1007\/978-3-319-18675-7"},{"volume-title":"Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS\u201913)","author":"K\u00fclt\u00fcrsay E.","unstructured":"E. K\u00fclt\u00fcrsay , M. Kandemir , A. Sivasubramaniam , and O. Mutlu . 2013. Evaluating STT-RAM as an energy-efficient main memory alternative . In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS\u201913) . 256\u2013267. E. K\u00fclt\u00fcrsay, M. Kandemir, A. Sivasubramaniam, and O. Mutlu. 2013. Evaluating STT-RAM as an energy-efficient main memory alternative. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS\u201913). 256\u2013267.","key":"e_1_2_1_22_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_23_1","DOI":"10.1145\/1555815.1555758"},{"doi-asserted-by":"publisher","key":"e_1_2_1_24_1","DOI":"10.1145\/3307650.3322232"},{"key":"e_1_2_1_25_1","volume-title":"Proceedings of the IEEE 19th International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems. 168\u2013175","author":"Lee S.","year":"2011","unstructured":"S. Lee , H. Bahn , and S. H. Noh . 2011. Characterizing memory write references for efficient management of hybrid PCM and DRAM memory . In Proceedings of the IEEE 19th International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems. 168\u2013175 . DOI:https:\/\/doi.org\/10.1109\/MASCOTS. 2011 .68 10.1109\/MASCOTS.2011.68 S. Lee, H. Bahn, and S. H. Noh. 2011. Characterizing memory write references for efficient management of hybrid PCM and DRAM memory. In Proceedings of the IEEE 19th International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems. 168\u2013175. DOI:https:\/\/doi.org\/10.1109\/MASCOTS.2011.68"},{"unstructured":"Micron Technology. 2011. 1.35V DDR3L SDRAM SODIMM. Technical Report MT16KTF51264HZ MT16KTF1G64HZ.  Micron Technology. 2011. 1.35V DDR3L SDRAM SODIMM. Technical Report MT16KTF51264HZ MT16KTF1G64HZ.","key":"e_1_2_1_26_1"},{"unstructured":"Micron Technology . 2015. DDR4 SDRAM. Technical Report MT40A2G4 MT40A1G8 MT40A512M16.  Micron Technology . 2015. DDR4 SDRAM. Technical Report MT40A2G4 MT40A1G8 MT40A512M16.","key":"e_1_2_1_27_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_28_1","DOI":"10.1109\/TPDS.2014.2324563"},{"doi-asserted-by":"publisher","key":"e_1_2_1_29_1","DOI":"10.1109\/IMW.2013.6582088"},{"key":"e_1_2_1_30_1","volume-title":"Hennessy","author":"Patterson David A.","year":"1990","unstructured":"David A. Patterson and John L . Hennessy . 1990 . Computer Architecture : A Quantitative Approach. Morgan Kaufmann Publishers Inc ., San Francisco, CA. David A. Patterson and John L. Hennessy. 1990. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers Inc., San Francisco, CA."},{"volume-title":"Proceedings of the IEEE Computer Society Symposium on VLSI. IEEE, 392\u2013397","author":"Poremba M.","unstructured":"M. Poremba and Y. Xie . 2012. NVMain: An architectural-level main memory simulator for emerging non-volatile memories . In Proceedings of the IEEE Computer Society Symposium on VLSI. IEEE, 392\u2013397 . M. Poremba and Y. Xie. 2012. NVMain: An architectural-level main memory simulator for emerging non-volatile memories. In Proceedings of the IEEE Computer Society Symposium on VLSI. IEEE, 392\u2013397.","key":"e_1_2_1_31_1"},{"volume-title":"Proceedings of the IEEE International Parallel and Distributed Processing Symposium (IPDPS\u201916)","author":"Pourshirazi B.","unstructured":"B. Pourshirazi and Z. Zhu . 2016. Refree: A refresh-free hybrid DRAM\/PCM main memory system . In Proceedings of the IEEE International Parallel and Distributed Processing Symposium (IPDPS\u201916) . IEEE, 566\u2013575. B. Pourshirazi and Z. Zhu. 2016. Refree: A refresh-free hybrid DRAM\/PCM main memory system. In Proceedings of the IEEE International Parallel and Distributed Processing Symposium (IPDPS\u201916). IEEE, 566\u2013575.","key":"e_1_2_1_32_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_33_1","DOI":"10.1109\/L-CA.2011.4"},{"unstructured":"Samsung Electronics. 2014. DDR4 SDRAM. Technical Report. Retrieved from: https:\/\/www.samsung.com\/semiconductor\/global.semi\/file\/resource\/2017\/11\/DDR4_Device_Operations_Rev11_Oct_14-0.pdf.  Samsung Electronics. 2014. DDR4 SDRAM. Technical Report. Retrieved from: https:\/\/www.samsung.com\/semiconductor\/global.semi\/file\/resource\/2017\/11\/DDR4_Device_Operations_Rev11_Oct_14-0.pdf.","key":"e_1_2_1_34_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_35_1","DOI":"10.1145\/3357526.3357538"},{"doi-asserted-by":"publisher","key":"e_1_2_1_37_1","DOI":"10.1109\/LCA.2016.2614497"},{"doi-asserted-by":"publisher","key":"e_1_2_1_38_1","DOI":"10.1145\/3061639.3062281"},{"unstructured":"MICRON Technologies.2006. DDR2 SDRAM. Technical Report MT47H512M4 MT47H256M8 MT47H128M16.  MICRON Technologies.2006. DDR2 SDRAM. Technical Report MT47H512M4 MT47H256M8 MT47H128M16.","key":"e_1_2_1_41_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_45_1","DOI":"10.1109\/TC.1981.1675811"},{"doi-asserted-by":"publisher","key":"e_1_2_1_46_1","DOI":"10.1109\/ICCAD.2011.6105369"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3458749","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3458749","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T17:49:06Z","timestamp":1750268946000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3458749"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,7,17]]},"references-count":39,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2021,12,31]]}},"alternative-id":["10.1145\/3458749"],"URL":"https:\/\/doi.org\/10.1145\/3458749","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"type":"print","value":"1544-3566"},{"type":"electronic","value":"1544-3973"}],"subject":[],"published":{"date-parts":[[2021,7,17]]},"assertion":[{"value":"2020-07-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-03-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-07-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}