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Syst."],"published-print":{"date-parts":[[2021,7,31]]},"abstract":"<jats:p>\n            A printed circuit board (PCB) provides necessary mechanical support to an electronic system and acts as a platform for connecting electronic components. Counterfeiting and in-field tampering of PCBs have become significant security concerns in the semiconductor industry as a result of increasing untrusted entities in the supply chain. These counterfeit components may result in performance degradation, profit reduction, and reputation risk for the manufacturers. While Integrated Circuit (IC) level authentication using physical unclonable functions (PUFs) has been widely investigated, countermeasures at the PCB level are scarce. These approaches either suffer from significant overhead issues, or opportunistic counterfeiters can breach them like clockwork. Besides, they cannot be extended to system-level (both chip and PCB together), and their applications are also limited to a specific purpose (i.e., either counterfeiting or tampering). In this article, we introduce\n            <jats:monospace>SILVerIn<\/jats:monospace>\n            , a novel systematic approach to verify the authenticity of all chips used in a PCB as well as the board for combating attacks such as counterfeiting, cloning, and in-field malicious modifications. We develop this approach by utilizing the existing boundary scan architecture (BSA) of modern ICs and PCBs. As a result, its implementation comes at a negligible (\u223c0.5%) hardware overhead.\n            <jats:monospace>SILVerIn<\/jats:monospace>\n            \u00a0is integrated into a PCB design during the manufacturing phase. We implement our technique on a custom hardware platform consisting of an FPGA and a microcontroller. We incorporate the industry-standard JTAG (Joint Test Action Group) interface to transmit test data into the BSA and perform hands-on measurement of supply current at both chip and PCB levels on 20 boards. We reconstruct these current values to digital signatures that exhibit high uniqueness, robustness, and randomness features. Our approach manifests strong reproducibility of signatures at different supply voltage levels, even with a low-resolution measurement setup.\n            <jats:monospace>SILVerIn<\/jats:monospace>\n            \u00a0also demonstrates a high resilience against machine learning-based modeling attacks, with an average prediction accuracy of \u223c51%. Finally, we conduct intentional alteration experiments by replacing the on-board FPGA to replicate the scenario of PCB tampering, and the results indicate successful detection of in-field modifications in a PCB.\n          <\/jats:p>","DOI":"10.1145\/3460232","type":"journal-article","created":{"date-parts":[[2021,6,30]],"date-time":"2021-06-30T19:26:58Z","timestamp":1625081218000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["SILVerIn: Systematic Integrity Verification of Printed Circuit Board Using JTAG Infrastructure"],"prefix":"10.1145","volume":"17","author":[{"given":"Shubhra Deb","family":"Paul","sequence":"first","affiliation":[{"name":"University of Florida"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Swarup","family":"Bhunia","sequence":"additional","affiliation":[{"name":"University of Florida"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2021,6,30]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"2010. 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