{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T04:08:15Z","timestamp":1773202095810,"version":"3.50.1"},"reference-count":48,"publisher":"Association for Computing Machinery (ACM)","issue":"5","license":[{"start":{"date-parts":[[2021,7,9]],"date-time":"2021-07-09T00:00:00Z","timestamp":1625788800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100011688","name":"ECSEL Joint Undertaking","doi-asserted-by":"crossref","award":["826610 (COMP4DRONES) and H2020-ECSEL-2017-2-783162 (FitOptiVis)"],"award-info":[{"award-number":["826610 (COMP4DRONES) and H2020-ECSEL-2017-2-783162 (FitOptiVis)"]}],"id":[{"id":"10.13039\/501100011688","id-type":"DOI","asserted-by":"crossref"}]},{"name":"European Union\u00e2..s Horizon 2020 research and innovation programme and Spain, Austria, Belgium, Czech Republic, France, Italy, Latvia, Netherlands"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2021,9,30]]},"abstract":"<jats:p>Advanced computations on embedded devices are nowadays a must in any application field. Often, to cope with such a need, embedded systems designers leverage on complex heterogeneous reconfigurable platforms that offer high performance, thanks to the possibility of specializing\/customizing some computing elements on board, and are usually flexible enough to be optimized at runtime. In this context, monitoring the system has gained increasing interest. Ideally, monitoring systems should be non-intrusive, serve several purposes, and provide aggregated information about the behavior of the different system components. However, current literature is not close to such ideality: For example, existing monitoring systems lack in being applicable to modern heterogeneous platforms. This work presents a hardware monitoring system that is intended to be minimally invasive on system performance and resources, composable, and capable of providing to the user homogeneous observability and transparent access to the different components of a heterogeneous computing platform, so system metrics can be easily computed from the aggregation of the collected information. Building on a previous work, this article is primarily focused on the extension of an existing hardware monitoring system to cover also specialized coprocessing units, and the assessment is done on a Xilinx FPGA-based System on Programmable Chip. Different explorations are presented to explain the level of customizability of the proposed hardware monitoring system, the tradeoffs available to the user, and the benefits with respect to standard de facto monitoring support made available by the targeted FPGA vendor.<\/jats:p>","DOI":"10.1145\/3461647","type":"journal-article","created":{"date-parts":[[2021,7,9]],"date-time":"2021-07-09T15:04:44Z","timestamp":1625843084000},"page":"1-34","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":19,"title":["A Composable Monitoring System for Heterogeneous Embedded Platforms"],"prefix":"10.1145","volume":"20","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0155-3788","authenticated-orcid":false,"given":"Giacomo","family":"Valente","sequence":"first","affiliation":[{"name":"Universit\u00e0 degli Studi dell\u2019Aquila, Italy"}]},{"given":"Tiziana","family":"Fanni","sequence":"additional","affiliation":[{"name":"Universit\u00e0 degli Studi di Sassari, Italy"}]},{"given":"Carlo","family":"Sau","sequence":"additional","affiliation":[{"name":"Universit\u00e0 degli Studi di Cagliari, Italy"}]},{"given":"Tania Di","family":"Mascio","sequence":"additional","affiliation":[{"name":"Universit\u00e0 degli Studi dell\u2019Aquila, Italy"}]},{"given":"Luigi","family":"Pomante","sequence":"additional","affiliation":[{"name":"Universit\u00e0 degli Studi dell\u2019Aquila, Italy"}]},{"given":"Francesca","family":"Palumbo","sequence":"additional","affiliation":[{"name":"Universit\u00e0 degli Studi di Sassari, Italy"}]}],"member":"320","published-online":{"date-parts":[[2021,7,9]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Lattice Semiconductor 2012-05. An FPGA \u201cCompanion\u201d in Smartphone Design - White Paper. Document ID 47335.  Lattice Semiconductor 2012-05. An FPGA \u201cCompanion\u201d in Smartphone Design - White Paper. Document ID 47335."},{"key":"e_1_2_1_2_1","unstructured":"2020. Jointer Open-source repository. Retrieved from https:\/\/github.com\/alkalir\/jointer.git.  2020. Jointer Open-source repository. Retrieved from https:\/\/github.com\/alkalir\/jointer.git."},{"key":"e_1_2_1_3_1","volume-title":"Conference on Computing Frontiers. 333\u2013338","author":"\u00a0al Zaid","year":"2019","unstructured":"Zaid Al-Ars et \u00a0al . 2019 . The FitOptiVis ECSEL project: Highly efficient distributed embedded image\/video processing in cyber-physical systems . In Conference on Computing Frontiers. 333\u2013338 . Zaid Al-Ars et\u00a0al. 2019. The FitOptiVis ECSEL project: Highly efficient distributed embedded image\/video processing in cyber-physical systems. In Conference on Computing Frontiers. 333\u2013338."},{"key":"e_1_2_1_4_1","volume-title":"Conference on Application-specific Systems, Architectures, and Processors. 61\u201368","author":"\u00a0al M. Aldham","year":"2011","unstructured":"M. Aldham et \u00a0al . 2011 . Low-cost hardware profiling of run-time and energy in FPGA embedded processors . In Conference on Application-specific Systems, Architectures, and Processors. 61\u201368 . M. Aldham et\u00a0al. 2011. Low-cost hardware profiling of run-time and energy in FPGA embedded processors. In Conference on Application-specific Systems, Architectures, and Processors. 61\u201368."},{"key":"e_1_2_1_5_1","volume-title":"Verification.","unstructured":"Altera. 2013-11. Design Debugging Using the SignalTap II Logic Analyzer. Quartus II Handbook v.13.1 . Vol. 3 : Verification. Altera. 2013-11. Design Debugging Using the SignalTap II Logic Analyzer. Quartus II Handbook v.13.1. Vol. 3: Verification."},{"key":"e_1_2_1_6_1","unstructured":"ARM. 2013-08. White Paper: CoreSight Technical Introduction A quickstart for designers. ARM-EPM-039795.  ARM. 2013-08. White Paper: CoreSight Technical Introduction A quickstart for designers. ARM-EPM-039795."},{"key":"e_1_2_1_7_1","unstructured":"ARM. 2020. AMBA AXI and ACE Protocol Specification AXI3 AXI4 and AXI4-Lite ACE and ACE-Lite. Retrieved from https:\/\/developer.arm.com\/documentation\/ihi0022\/e\/.  ARM. 2020. AMBA AXI and ACE Protocol Specification AXI3 AXI4 and AXI4-Lite ACE and ACE-Lite. Retrieved from https:\/\/developer.arm.com\/documentation\/ihi0022\/e\/."},{"key":"#cr-split#-e_1_2_1_8_1.1","doi-asserted-by":"crossref","unstructured":"D. Arora S. Ravi A. Raghunathan and N. K. Jha. 2005. Secure embedded processing through hardware-assisted run-time monitoring. In Design Automation and Test in Europe. 178-183 Vol. 1. DOI:DOI:https:\/\/doi.org\/10.1109\/DATE.2005.266 10.1109\/DATE.2005.266","DOI":"10.1109\/DATE.2005.266"},{"key":"#cr-split#-e_1_2_1_8_1.2","doi-asserted-by":"crossref","unstructured":"D. Arora S. Ravi A. Raghunathan and N. K. Jha. 2005. Secure embedded processing through hardware-assisted run-time monitoring. In Design Automation and Test in Europe. 178-183 Vol. 1. DOI:DOI:https:\/\/doi.org\/10.1109\/DATE.2005.266","DOI":"10.1109\/DATE.2005.266"},{"key":"e_1_2_1_9_1","volume-title":"Symposium on Field-programmable Custom Computing Machines. IEEE Computer Society, 93\u201396","author":"Brant Alexander","unstructured":"Alexander Brant and Guy G. F. Lemieux . 2012. ZUMA: An open FPGA overlay architecture . In Symposium on Field-programmable Custom Computing Machines. IEEE Computer Society, 93\u201396 . Alexander Brant and Guy G. F. Lemieux. 2012. ZUMA: An open FPGA overlay architecture. In Symposium on Field-programmable Custom Computing Machines. IEEE Computer Society, 93\u201396."},{"key":"e_1_2_1_10_1","volume-title":"LegUp: An open-source high-level synthesis tool for FPGA-based processor\/accelerator systems. ACM Trans. Embed. Comput. Syst. 13 (09","author":"\u00a0al Andrew Canis","year":"2013","unstructured":"Andrew Canis et \u00a0al . 2013. LegUp: An open-source high-level synthesis tool for FPGA-based processor\/accelerator systems. ACM Trans. Embed. Comput. Syst. 13 (09 2013 ). Andrew Canis et\u00a0al. 2013. LegUp: An open-source high-level synthesis tool for FPGA-based processor\/accelerator systems. ACM Trans. Embed. Comput. Syst. 13 (09 2013)."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2018.07.007"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1016\/0262-8856(84)90049-0"},{"key":"e_1_2_1_13_1","volume-title":"Automation Test in Europe Conference Exhibition (DATE\u201917)","author":"\u00a0al N. C.","year":"2017","unstructured":"N. C. Doyle et \u00a0al . 2017 . Performance impacts and limitations of hardware memory access trace collection. In Design , Automation Test in Europe Conference Exhibition (DATE\u201917) , 2017. 506\u2013511. N. C. Doyle et\u00a0al. 2017. Performance impacts and limitations of hardware memory access trace collection. In Design, Automation Test in Europe Conference Exhibition (DATE\u201917), 2017. 506\u2013511."},{"key":"e_1_2_1_14_1","volume-title":"Conference on ReConFigurable Computing and FPGAs. IEEE, 1\u20138.","author":"\u00a0al Tiziana Fanni","year":"2018","unstructured":"Tiziana Fanni et \u00a0al . 2018 . Multi-grain reconfiguration for advanced adaptivity in cyber-physical systems . In Conference on ReConFigurable Computing and FPGAs. IEEE, 1\u20138. Tiziana Fanni et\u00a0al. 2018. Multi-grain reconfiguration for advanced adaptivity in cyber-physical systems. In Conference on ReConFigurable Computing and FPGAs. IEEE, 1\u20138."},{"key":"e_1_2_1_15_1","volume-title":"Workshop on FPGAs for Software Programmers. 1\u201310","author":"\u00a0al T. Fanni","year":"2019","unstructured":"T. Fanni et \u00a0al . 2019 . Run-time performance monitoring of heterogenous Hw\/Sw platforms using PAPI . In Workshop on FPGAs for Software Programmers. 1\u201310 . T. Fanni et\u00a0al. 2019. Run-time performance monitoring of heterogenous Hw\/Sw platforms using PAPI. In Workshop on FPGAs for Software Programmers. 1\u201310."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2565204"},{"key":"e_1_2_1_17_1","first-page":"384","article-title":"A unified design flow to automatically generate on-chip monitors during high-level synthesis of hardware accelerators","volume":"36","author":"\u00a0al M. B.","year":"2017","unstructured":"M. B. Hammouda et \u00a0al . 2017 . A unified design flow to automatically generate on-chip monitors during high-level synthesis of hardware accelerators . IEEE Trans. Comput.-aided Des. Integ. Circ. Syst. 36 , 3 (2017), 384 \u2013 397 . M. B. Hammouda et\u00a0al. 2017. A unified design flow to automatically generate on-chip monitors during high-level synthesis of hardware accelerators. IEEE Trans. Comput.-aided Des. Integ. Circ. Syst. 36, 3 (2017), 384\u2013397.","journal-title":"IEEE Trans. Comput.-aided Des. Integ. Circ. Syst."},{"key":"e_1_2_1_18_1","volume-title":"Performance Evaluation and Benchmarking","author":"John Lizy Kurian","unstructured":"Lizy Kurian John and Lieven Eeckhout . 2006. Performance Evaluation and Benchmarking . Taylor & Francis Group - CRC Press , Boca Raton . Lizy Kurian John and Lieven Eeckhout. 2006. Performance Evaluation and Benchmarking. Taylor & Francis Group - CRC Press, Boca Raton."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2442087.2442088"},{"key":"e_1_2_1_20_1","volume-title":"HERO: Heterogeneous embedded research platform for exploring RISC-V manycore accelerators on FPGA. CoRR abs\/1712.06497","author":"\u00a0al Andreas Kurth","year":"2017","unstructured":"Andreas Kurth et \u00a0al . 2017 . HERO: Heterogeneous embedded research platform for exploring RISC-V manycore accelerators on FPGA. CoRR abs\/1712.06497 (2017). Andreas Kurth et\u00a0al. 2017. HERO: Heterogeneous embedded research platform for exploring RISC-V manycore accelerators on FPGA. CoRR abs\/1712.06497 (2017)."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2717310"},{"key":"e_1_2_1_22_1","volume-title":"Conference on Advances in Computing, Electronics and Electrical Technology.","author":"\u00a0al Xiangwei Li","year":"2018","unstructured":"Xiangwei Li et \u00a0al . 2018 . FPGA overlays: Hardware-based computing for the masses . In Conference on Advances in Computing, Electronics and Electrical Technology. Xiangwei Li et\u00a0al. 2018. FPGA overlays: Hardware-based computing for the masses. In Conference on Advances in Computing, Electronics and Electrical Technology."},{"key":"e_1_2_1_23_1","article-title":"Time-multiplexed FPGA overlay architectures: A survey","volume":"24","author":"Li Xiangwei","year":"2019","unstructured":"Xiangwei Li and Douglas L. Maskell . 2019 . Time-multiplexed FPGA overlay architectures: A survey . ACM Trans. Des. Autom. Electr. Syst. 24 , 5 (2019), 54:1\u201354:19. Xiangwei Li and Douglas L. Maskell. 2019. Time-multiplexed FPGA overlay architectures: A survey. ACM Trans. Des. Autom. Electr. Syst. 24, 5 (2019), 54:1\u201354:19.","journal-title":"ACM Trans. Des. Autom. Electr. Syst."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/3310273.3323423"},{"key":"e_1_2_1_25_1","volume-title":"International Conference on Field-programmable Technology. 409\u2013412","author":"\u00a0al E. Matthews","year":"2010","unstructured":"E. Matthews et \u00a0al . 2010 . A configurable framework for investigating workload execution . In International Conference on Field-programmable Technology. 409\u2013412 . E. Matthews et\u00a0al. 2010. A configurable framework for investigating workload execution. In International Conference on Field-programmable Technology. 409\u2013412."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2010.03.001"},{"key":"e_1_2_1_27_1","volume-title":"Workshop on Intelligent Solutions in Embedded Systems. 29\u201334","author":"\u00a0al A. Moro","year":"2015","unstructured":"A. Moro et \u00a0al . 2015 . Hardware performance sniffers for embedded systems profiling . In Workshop on Intelligent Solutions in Embedded Systems. 29\u201334 . A. Moro et\u00a0al. 2015. Hardware performance sniffers for embedded systems profiling. In Workshop on Intelligent Solutions in Embedded Systems. 29\u201334."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD51259.2020.00029"},{"key":"e_1_2_1_29_1","volume-title":"Symposium on VLSI Design and Test. 1\u20136.","author":"Nadimpalli P. K.","unstructured":"P. K. Nadimpalli and S. K. Roy . 2016. An efficient FPGA-based function profiler for embedded system applications . In Symposium on VLSI Design and Test. 1\u20136. P. K. Nadimpalli and S. K. Roy. 2016. An efficient FPGA-based function profiler for embedded system applications. In Symposium on VLSI Design and Test. 1\u20136."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2614347"},{"key":"e_1_2_1_31_1","volume-title":"Reliable Software Technologies \u2013 Ada-Europe","author":"\u00a0al Geoffrey Nelissen","year":"2015","unstructured":"Geoffrey Nelissen et \u00a0al . 2015. A novel run-time monitoring architecture for safe and efficient inline monitoring . In Reliable Software Technologies \u2013 Ada-Europe 2015 . Springer International Publishing , Cham , 66\u201382. Geoffrey Nelissen et\u00a0al. 2015. A novel run-time monitoring architecture for safe and efficient inline monitoring. In Reliable Software Technologies \u2013 Ada-Europe 2015. Springer International Publishing, Cham, 66\u201382."},{"key":"e_1_2_1_32_1","volume-title":"Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation. Cham, 416\u2013428","author":"\u00a0al Francesca Palumbo","year":"2019","unstructured":"Francesca Palumbo et \u00a0al . 2019 . Hardware\/software self-adaptation in CPS: The CERBERO project approach . In Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation. Cham, 416\u2013428 . Francesca Palumbo et\u00a0al. 2019. Hardware\/software self-adaptation in CPS: The CERBERO project approach. In Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation. Cham, 416\u2013428."},{"key":"e_1_2_1_33_1","unstructured":"PAPI. 2020. Performance API. Retrieved from http:\/\/icl.utk.edu\/papi\/.  PAPI. 2020. Performance API. Retrieved from http:\/\/icl.utk.edu\/papi\/."},{"key":"e_1_2_1_34_1","volume-title":"Symposium on Power and Timing Modeling, Optimization and Simulation. 123\u2013128","author":"\u00a0al G. Patrigeon","year":"2018","unstructured":"G. Patrigeon et \u00a0al . 2018 . FPGA-based platform for fast accurate evaluation of ultra low power SoC . In Symposium on Power and Timing Modeling, Optimization and Simulation. 123\u2013128 . G. Patrigeon et\u00a0al. 2018. FPGA-based platform for fast accurate evaluation of ultra low power SoC. In Symposium on Power and Timing Modeling, Optimization and Simulation. 123\u2013128."},{"key":"e_1_2_1_35_1","volume-title":"Conference on Hardware\/Software Codesign and System Synthesis. 1\u201310","author":"\u00a0al E. A.","year":"2019","unstructured":"E. A. Rambo et \u00a0al . 2019 . The information processing factory: A paradigm for life cycle management of dependable systems . In Conference on Hardware\/Software Codesign and System Synthesis. 1\u201310 . E. A. Rambo et\u00a0al. 2019. The information processing factory: A paradigm for life cycle management of dependable systems. In Conference on Hardware\/Software Codesign and System Synthesis. 1\u201310."},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.3390\/s18061877"},{"key":"e_1_2_1_37_1","volume-title":"Ahmad et al","author":"Sadek","year":"2018","unstructured":"Sadek , Ahmad et al . 2018 . Supporting utilities for heterogeneous embedded image processing platforms (STHEM): An overview. In Applied Reconfigurable Computing. Architectures, Tools, and Applications. Springer International Publishing , Cham, 737\u2013749. Sadek, Ahmad et al. 2018. Supporting utilities for heterogeneous embedded image processing platforms (STHEM): An overview. In Applied Reconfigurable Computing. Architectures, Tools, and Applications. Springer International Publishing, Cham, 737\u2013749."},{"key":"e_1_2_1_38_1","first-page":"1","article-title":"Automated design flow for multi-functional dataflow-based platforms","volume":"85","author":"\u00a0al C. Sau","year":"2016","unstructured":"C. Sau et \u00a0al . 2016 . Automated design flow for multi-functional dataflow-based platforms . J. Sign. Process. Syst. 85 , 1 (Oct. 2016), 143\u2013165. C. Sau et\u00a0al. 2016. Automated design flow for multi-functional dataflow-based platforms. J. Sign. Process. Syst. 85, 1 (Oct. 2016), 143\u2013165.","journal-title":"J. Sign. Process. Syst."},{"key":"e_1_2_1_39_1","volume-title":"Conference on Digital System Design. 86\u201393","author":"\u00a0al T. Scheipel","year":"2017","unstructured":"T. Scheipel et \u00a0al . 2017 . System-aware performance monitoring unit for RISC-V architectures . In Conference on Digital System Design. 86\u201393 . T. Scheipel et\u00a0al. 2017. System-aware performance monitoring unit for RISC-V architectures. In Conference on Digital System Design. 86\u201393."},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3358200"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/3206213"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.5555\/3283568.3283575"},{"key":"e_1_2_1_43_1","volume-title":"Conference on Field Programmable Logic and Applications. IEEE Computer Society, 131\u2013138","author":"\u00a0al Anuj Vaishnav","year":"2018","unstructured":"Anuj Vaishnav et \u00a0al . 2018 . A survey on FPGA virtualization . In Conference on Field Programmable Logic and Applications. IEEE Computer Society, 131\u2013138 . Anuj Vaishnav et\u00a0al. 2018. A survey on FPGA virtualization. In Conference on Field Programmable Logic and Applications. IEEE Computer Society, 131\u2013138."},{"key":"e_1_2_1_44_1","volume-title":"Conference on Parallel, Distributed, and Network-based Processing. 373\u2013376","author":"\u00a0al G. Valente","year":"2016","unstructured":"G. Valente et \u00a0al . 2016 . A flexible profiling sub-system for reconfigurable logic architectures . In Conference on Parallel, Distributed, and Network-based Processing. 373\u2013376 . G. Valente et\u00a0al. 2016. A flexible profiling sub-system for reconfigurable logic architectures. In Conference on Parallel, Distributed, and Network-based Processing. 373\u2013376."},{"key":"e_1_2_1_45_1","unstructured":"Xilinx. 2017-06-7. System Integrated Logic Analyzer v1.0 LogiCORE IP Product Guide PG261.  Xilinx. 2017-06-7. System Integrated Logic Analyzer v1.0 LogiCORE IP Product Guide PG261."},{"key":"e_1_2_1_46_1","unstructured":"Xilinx. 2017-10-4. AXI Performance Monitor v5.0 LogiCORE IP Product Guide PG037. https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/system_ila\/v1_0\/pg261-system-ila.pdf.  Xilinx. 2017-10-4. AXI Performance Monitor v5.0 LogiCORE IP Product Guide PG037. https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/system_ila\/v1_0\/pg261-system-ila.pdf."},{"key":"e_1_2_1_47_1","unstructured":"Xilinx. 2020. Zynq7000 SoC Technical Reference Manual. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/axi_perf_mon\/v5_0\/pg037_axi_perf_mon.pdf.  Xilinx. 2020. Zynq7000 SoC Technical Reference Manual. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/axi_perf_mon\/v5_0\/pg037_axi_perf_mon.pdf."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3461647","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3461647","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:49:04Z","timestamp":1750193344000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3461647"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,7,9]]},"references-count":48,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2021,9,30]]}},"alternative-id":["10.1145\/3461647"],"URL":"https:\/\/doi.org\/10.1145\/3461647","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,7,9]]},"assertion":[{"value":"2020-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-07-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}