{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,14]],"date-time":"2026-04-14T15:59:03Z","timestamp":1776182343138,"version":"3.50.1"},"reference-count":65,"publisher":"Association for Computing Machinery (ACM)","issue":"5","license":[{"start":{"date-parts":[[2021,7,9]],"date-time":"2021-07-09T00:00:00Z","timestamp":1625788800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2021,9,30]]},"abstract":"<jats:p>Nowadays, static power consumption in chip multiprocessor (CMP) is the most crucial concern of chip designers. Power-gating is an effective approach to mitigate static power consumption particularly in low utilization. Network-on-Chip (NoC) as the backbone of multi- and many-core chips has no exception. Previous state-of-the-art techniques in power-gating desire to decrease static power consumption alongside the lack of diminution in performance of NoC. However, maintaining the performance and utilization of the power-gating approach has not yet been addressed very well. In this article, we propose TAMA (Turn-Aware Mapping &amp; Architecture) as an effective method to boost the performance of the TooT method that was only powering on a router during turning pass or packet injection. In other words, in the TooT method, straight and eject packets pass the router via a bypass route without powering on the router. By employing meta-heuristic approaches (Genetic and Ant Colony algorithms), we develop a specific application mapping that attempts to decrease the number of turns through interconnection networks. Accordingly, the average latency of packet transmission decreases due to fewer turns. Also, by powering on turn routers in advance with lightweight hardware, the latency of sending packets diminishes. The experimental results demonstrate that our proposed approach, i.e., TAMA achieves more than 13% reduction in packet latency of NoC in comparison with TooT. Besides the packet latency, the power consumption of TAMA is reduced by about 87% compared to the traditional approach.<\/jats:p>","DOI":"10.1145\/3462700","type":"journal-article","created":{"date-parts":[[2021,7,9]],"date-time":"2021-07-09T15:04:44Z","timestamp":1625843084000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":21,"title":["TAMA"],"prefix":"10.1145","volume":"20","author":[{"given":"Rashid","family":"Aligholipour","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Isfahan, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0240-2826","authenticated-orcid":false,"given":"Mohammad","family":"Baharloo","sequence":"additional","affiliation":[{"name":"School of Computer Sciences, Institute for Research in FundamentalSciences (IPM) &amp; Department of Electrical and Computer Engineering, Qom University of Technology, Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Behnam","family":"Farzaneh","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Isfahan University of Technology, Tehran, Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Meisam","family":"Abdollahi","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ahmad","family":"Khonsari","sequence":"additional","affiliation":[{"name":"School of Computer Sciences, Institute for Research in Fundamental Sciences (IPM) &amp; Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2021,7,9]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"23rd International Conference on Field-programmable Logic and Applications. IEEE, 1\u20138.","author":"Mohamed"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2020.106559"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2020.06.016"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2017.07.004"},{"key":"e_1_2_1_5_1","volume-title":"IEEE International Symposium on Performance Analysis of Systems and Software. IEEE, 33\u201342","author":"Agarwal Niket"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00049"},{"key":"e_1_2_1_7_1","first-page":"4","article-title":"Review of network on chip architectures","volume":"10","author":"Javed Sethi Muhammad Athar","year":"2017","journal-title":"Rec. Adv. Electric. Electron. Eng."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2020.106578"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2018.09.001"},{"key":"e_1_2_1_10_1","doi-asserted-by":"crossref","unstructured":"Mohammad Baharloo Ahmad Khonsari Mahdi Dolati Pouya Shiri Masoumeh Ebrahimi and Dara Rahmati. 2020. Traffic-aware performance optimization in Real-time wireless network on chip. Nano Commun. Netw. (2020) 100321.  Mohammad Baharloo Ahmad Khonsari Mahdi Dolati Pouya Shiri Masoumeh Ebrahimi and Dara Rahmati. 2020. Traffic-aware performance optimization in Real-time wireless network on chip. Nano Commun. Netw. (2020) 100321.","DOI":"10.1016\/j.nancom.2020.100321"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICNAS.2019.8807815"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523070"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS48704.2020.9184540"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2017.06.004"},{"key":"e_1_2_1_17_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 338\u2013343","author":"Owen Chen Chia-Hsin","year":"2013"},{"key":"e_1_2_1_18_1","volume-title":"45th IEEE\/ACM International Symposium on Microarchitecture. IEEE, 270\u2013281","author":"Chen Lizhong"},{"key":"e_1_2_1_19_1","volume-title":"IEEE 20th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 296\u2013307","author":"Chen Lizhong"},{"key":"e_1_2_1_20_1","volume-title":"IEEE 21st International Symposium on High Performance Computer Architecture (HPCA). IEEE, 378\u2013389","author":"Chen Lizhong"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2016.03.006"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485950"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665680"},{"key":"e_1_2_1_24_1","doi-asserted-by":"crossref","unstructured":"Fatemeh Dehghani Siamak Mohammadi Behrang Barekatain and Meisam Abdollahi. 2020. Power loss analysis in thermally-tuned nanophotonic switch for on-chip interconnect. Nano Commun. Netw. (2020) 100323.  Fatemeh Dehghani Siamak Mohammadi Behrang Barekatain and Meisam Abdollahi. 2020. Power loss analysis in thermally-tuned nanophotonic switch for on-chip interconnect. Nano Commun. Netw. (2020) 100323.","DOI":"10.1016\/j.nancom.2020.100323"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927203"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/3477.484436"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/3200201"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000108"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/3130218.3130231"},{"key":"e_1_2_1_30_1","volume-title":"IEEE\/ACM International Symposium on Low Power Electronics and Design. IEEE, 1\u20136.","author":"Farrokhbakht Hossein"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3313231.3352362"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2016.7579326"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_2_1_34_1","volume-title":"3rd International Workshop on Network on Chip Architectures. 31\u201336","author":"Hestness Joel"},{"key":"e_1_2_1_35_1","volume-title":"et\u00a0al","author":"Holland John Henry","year":"1992"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.5555\/1320302.1320837"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2016.04.006"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2016.00118"},{"key":"e_1_2_1_39_1","first-page":"225","article-title":"The traveling salesman problem","volume":"7","author":"J\u00fcnger Michael","year":"1995","journal-title":"Handb. Oper. Res. Manag. Sci."},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3386263.3406900"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2844365"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2015.12.001"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2020.3022920"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2017.90"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2017.91"},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/2994133.2994138"},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/3322899"},{"key":"e_1_2_1_48_1","volume-title":"13th International Multi-Conference on Computing in Global Information Technology. IARIA.","author":"Ofori-Attah Emmanuel","year":"2018"},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593187"},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICED.2016.7804649"},{"key":"e_1_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS48704.2020.9184490"},{"key":"e_1_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/3313231.3352377"},{"key":"e_1_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351580"},{"key":"e_1_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/3291606"},{"key":"e_1_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1587\/elex.6.1737"},{"key":"e_1_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108121"},{"key":"e_1_2_1_57_1","volume-title":"IEEE Computer Society Symposium on VLSI (ISVLSI). IEEE, 14\u201319","author":"Mohd Sayuti M. Norazizi Sham","year":"2013"},{"key":"e_1_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.31"},{"key":"e_1_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00058"},{"key":"e_1_2_1_60_1","volume-title":"Designing 2D and 3D Network-on-Chip Architectures","author":"Tatas Konstantinos"},{"key":"e_1_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"e_1_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1145\/2886781"},{"key":"e_1_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1145\/225830.223990"},{"key":"e_1_2_1_64_1","volume-title":"IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 309\u2013320","author":"Yao Yuan","year":"2016"},{"key":"e_1_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1145\/2751561"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3462700","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3462700","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:19:03Z","timestamp":1750191543000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3462700"}},"subtitle":["Turn-aware Mapping and Architecture \u2013 A Power-efficient Network-on-Chip Approach"],"short-title":[],"issued":{"date-parts":[[2021,7,9]]},"references-count":65,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2021,9,30]]}},"alternative-id":["10.1145\/3462700"],"URL":"https:\/\/doi.org\/10.1145\/3462700","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,7,9]]},"assertion":[{"value":"2020-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-07-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}