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Embed. Comput. Syst."],"published-print":{"date-parts":[[2021,9,30]]},"abstract":"<jats:p>Adoption of multi- and many-core processors in real-time systems has so far been slowed down, if not totally barred, due do the difficulty in providing analytical real-time guarantees on worst-case execution times. The Predictable Execution Model (PREM) has been proposed to solve this problem, but its practical support requires significant code refactoring, a task better suited for a compilation tool chain than human programmers. Implementing a PREM compiler presents significant challenges to conform to PREM requirements, such as guaranteed upper bounds on memory footprint and the generation of efficient schedulable non-preemptive regions. This article presents a comprehensive description on how a PREM compiler can be implemented, based on several years of experience from the community. We provide accumulated insights on how to best balance conformance to real-time requirements and performance and present novel techniques that extend the applicability from simple benchmark suites to real-world applications. We show that code transformed by the PREM compiler enables timing predictable execution on modern commercial off-the-shelf hardware, providing novel insights on how PREM can protect 99.4% of memory accesses on random replacement policy caches at only 16% performance loss on benchmarks from the PolyBench benchmark suite. Finally, we show that the requirements imposed on the programming model are well-aligned with current coding guidelines for timing critical software, promoting easy adoption.<\/jats:p>","DOI":"10.1145\/3465370","type":"journal-article","created":{"date-parts":[[2021,7,29]],"date-time":"2021-07-29T11:11:02Z","timestamp":1627557062000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["The Predictable Execution Model in Practice"],"prefix":"10.1145","volume":"20","author":[{"given":"Bj\u00f6rn","family":"Forsberg","sequence":"first","affiliation":[{"name":"ETH Z\u00fcrich, Switzerland"}]},{"given":"Marco","family":"Solieri","sequence":"additional","affiliation":[{"name":"University of Modena and Reggio Emilia, Italy"}]},{"given":"Marko","family":"Bertogna","sequence":"additional","affiliation":[{"name":"University of Modena and Reggio Emilia, Italy"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich, Switzerland and University of Bologna, Italy"}]},{"given":"Andrea","family":"Marongiu","sequence":"additional","affiliation":[{"name":"University of Modena and Reggio Emilia, Italy"}]}],"member":"320","published-online":{"date-parts":[[2021,7,29]]},"reference":[{"key":"e_1_2_1_1_1","first-page":"5s","article-title":"Cache locking content selection algorithms for ARINC-653 compliant RTOS","volume":"18","author":"Aurora Dugo Alexy Torres","year":"2019","unstructured":"Alexy Torres Aurora Dugo , Jean-Baptiste Lefoul , Felipe Gohring De Magalhaes , Dahman Assal , and Gabriela Nicolescu . 2019 . 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