{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T10:05:13Z","timestamp":1781258713237,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":83,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,10,17]],"date-time":"2021-10-17T00:00:00Z","timestamp":1634428800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Spanish Ministry of Science and Technology","award":["PID2019-107255GB"],"award-info":[{"award-number":["PID2019-107255GB"]}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1912617"],"award-info":[{"award-number":["1912617"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2936.001"],"award-info":[{"award-number":["2936.001"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Spanish Ministry of Economy, Industry and Competitiveness","award":["RYC-2017-23269, FJCI-2016-30984, PRE2018-087046"],"award-info":[{"award-number":["RYC-2017-23269, FJCI-2016-30984, PRE2018-087046"]}]},{"DOI":"10.13039\/501100002809","name":"Generalitat de Catalunya","doi-asserted-by":"publisher","award":["2017-SGR-1414"],"award-info":[{"award-number":["2017-SGR-1414"]}],"id":[{"id":"10.13039\/501100002809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,10,18]]},"DOI":"10.1145\/3466752.3480049","type":"proceedings-article","created":{"date-parts":[[2021,10,17]],"date-time":"2021-10-17T19:16:55Z","timestamp":1634498215000},"page":"1138-1153","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Morrigan: A Composite Instruction TLB Prefetcher"],"prefix":"10.1145","author":[{"given":"Georgios","family":"Vavouliotis","sequence":"first","affiliation":[{"name":"Universitat Politecnica de Catalunya \/ Barcelona Supercomputing Center, Greece"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lluc","family":"Alvarez","sequence":"additional","affiliation":[{"name":"Universitat Politecnica de Catalunya \/ Barcelona Supercomputing Center, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Boris","family":"Grot","sequence":"additional","affiliation":[{"name":"University of Edinburgh, United Kingdom"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Daniel","family":"Jim\u00e9nez","sequence":"additional","affiliation":[{"name":"Texas A&M University, United States of America"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Marc","family":"Casas","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2021,10,17]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"1996. Before Memory Was Virtual. http:\/\/denninginstitute.com\/pjd\/PUBS\/bvm.pdf.  1996. Before Memory Was Virtual. http:\/\/denninginstitute.com\/pjd\/PUBS\/bvm.pdf."},{"key":"e_1_3_2_1_2_1","volume-title":"SPEC CPU 2006","year":"2006","unstructured":"2006. SPEC CPU 2006 . https:\/\/www.spec.org\/cpu 2006 \/. 2006. SPEC CPU 2006. https:\/\/www.spec.org\/cpu2006\/."},{"key":"e_1_3_2_1_3_1","unstructured":"2008. The Locality Principle. https:\/\/denninginstitute.com\/pjd\/PUBS\/ENC\/locality08.pdf.  2008. The Locality Principle. https:\/\/denninginstitute.com\/pjd\/PUBS\/ENC\/locality08.pdf."},{"key":"e_1_3_2_1_4_1","unstructured":"2010. Huge Pages and libhugetlbfs. https:\/\/lwn.net\/Articles\/374424\/.  2010. Huge Pages and libhugetlbfs. https:\/\/lwn.net\/Articles\/374424\/."},{"key":"e_1_3_2_1_5_1","unstructured":"2012. Sandy Bridge - Microarchitectures. https:\/\/en.wikichip.org\/wiki\/intel\/microarchitectures\/sandy_bridge_(client).  2012. Sandy Bridge - Microarchitectures. https:\/\/en.wikichip.org\/wiki\/intel\/microarchitectures\/sandy_bridge_(client)."},{"key":"e_1_3_2_1_6_1","unstructured":"2013. Haswell - Microarchitectures - Intel. https:\/\/en.wikichip.org\/wiki\/intel\/microarchitectures\/haswell_(client).  2013. Haswell - Microarchitectures - Intel. https:\/\/en.wikichip.org\/wiki\/intel\/microarchitectures\/haswell_(client)."},{"key":"e_1_3_2_1_7_1","unstructured":"2014. Using Intel VTune Amplifier XE to tune software on the 6th generation Intel Core processor family. https:\/\/software.intel.com\/content\/dam\/develop\/external\/us\/en\/documents\/using-intel-vtune-amplifier-xe-on-6th-generation-intel-core-processors-1-0.pdf.  2014. Using Intel VTune Amplifier XE to tune software on the 6th generation Intel Core processor family. https:\/\/software.intel.com\/content\/dam\/develop\/external\/us\/en\/documents\/using-intel-vtune-amplifier-xe-on-6th-generation-intel-core-processors-1-0.pdf."},{"key":"e_1_3_2_1_8_1","unstructured":"2015-2021. ARMv8 Architecture Reference Manual. ARM.https:\/\/developer.arm.com\/documentation\/ddi0553\/bp.  2015-2021. ARMv8 Architecture Reference Manual. ARM.https:\/\/developer.arm.com\/documentation\/ddi0553\/bp."},{"key":"e_1_3_2_1_9_1","unstructured":"2017. Coffee Lake - Microarchitectures. https:\/\/en.wikichip.org\/wiki\/intel\/microarchitectures\/coffee_lake.  2017. Coffee Lake - Microarchitectures. https:\/\/en.wikichip.org\/wiki\/intel\/microarchitectures\/coffee_lake."},{"key":"e_1_3_2_1_10_1","volume-title":"SPEC CPU 2017","year":"2017","unstructured":"2017. SPEC CPU 2017 . https:\/\/www.spec.org\/cpu 2017 \/. 2017. SPEC CPU 2017. https:\/\/www.spec.org\/cpu2017\/."},{"key":"e_1_3_2_1_11_1","unstructured":"2017. The RISC-V Instruction Set Manual. https:\/\/content.riscv.org\/wp-content\/uploads\/2017\/05\/riscv-privileged-v1.10.pdf.  2017. The RISC-V Instruction Set Manual. https:\/\/content.riscv.org\/wp-content\/uploads\/2017\/05\/riscv-privileged-v1.10.pdf."},{"key":"e_1_3_2_1_12_1","unstructured":"2018. Intel. 5-Level Paging and 5-Level EPT. https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/download\/5-level-paging-and-5-level-ept-white-paper.html.  2018. Intel. 5-Level Paging and 5-Level EPT. https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/download\/5-level-paging-and-5-level-ept-white-paper.html."},{"key":"e_1_3_2_1_13_1","unstructured":"2020. A Principled Technologies report: Hands-on testing. Real-world results.https:\/\/www.principledtechnologies.com\/Intel\/Xeon-8272CL-Microsoft-Azure-WordPress-science-0920.pdf.  2020. A Principled Technologies report: Hands-on testing. Real-world results.https:\/\/www.principledtechnologies.com\/Intel\/Xeon-8272CL-Microsoft-Azure-WordPress-science-0920.pdf."},{"key":"e_1_3_2_1_14_1","unstructured":"2020. Championship Value Prediction (CVP). https:\/\/www.microarch.org\/cvp1\/.  2020. Championship Value Prediction (CVP). https:\/\/www.microarch.org\/cvp1\/."},{"key":"e_1_3_2_1_15_1","unstructured":"2020. ChampSim. https:\/\/crc2.ece.tamu.edu\/. [Online].  2020. ChampSim. https:\/\/crc2.ece.tamu.edu\/. [Online]."},{"key":"e_1_3_2_1_16_1","unstructured":"2020. iTLB multihit. https:\/\/www.kernel.org\/doc\/html\/latest\/admin-guide\/hw-vuln\/multihit.html.  2020. iTLB multihit. https:\/\/www.kernel.org\/doc\/html\/latest\/admin-guide\/hw-vuln\/multihit.html."},{"key":"e_1_3_2_1_17_1","unstructured":"2020. perf: Linux profiling with performance counters.https:\/\/perf.wiki.kernel.org.  2020. perf: Linux profiling with performance counters.https:\/\/perf.wiki.kernel.org."},{"key":"e_1_3_2_1_18_1","unstructured":"2020. perl-Net-Amazon. https:\/\/ppisar.fedorapeople.org\/perl_rebuild\/scratch\/latest\/packages\/perl-Net-Amazon\/hw_info.log.  2020. perl-Net-Amazon. https:\/\/ppisar.fedorapeople.org\/perl_rebuild\/scratch\/latest\/packages\/perl-Net-Amazon\/hw_info.log."},{"key":"e_1_3_2_1_19_1","unstructured":"2020. perl-Net-Amazon-EC2. https:\/\/ppisar.fedorapeople.org\/perl_rebuild\/scratch\/latest\/packages\/perl-Net-Amazon-EC2\/hw_info.log.  2020. perl-Net-Amazon-EC2. https:\/\/ppisar.fedorapeople.org\/perl_rebuild\/scratch\/latest\/packages\/perl-Net-Amazon-EC2\/hw_info.log."},{"key":"e_1_3_2_1_20_1","unstructured":"2020. perl-Net-Amazon-S3. https:\/\/ppisar.fedorapeople.org\/perl_rebuild\/scratch\/latest\/packages\/perl-Net-Amazon-S3\/hw_info.log.  2020. perl-Net-Amazon-S3. https:\/\/ppisar.fedorapeople.org\/perl_rebuild\/scratch\/latest\/packages\/perl-Net-Amazon-S3\/hw_info.log."},{"key":"e_1_3_2_1_21_1","unstructured":"2020. Public clouds and vulnerable CPUs: are we secure?https:\/\/archive.fosdem.org\/2020\/schedule\/event\/vai_pubic_clouds_and_vulnerable_cpus\/attachments\/slides\/3650\/export\/events\/attachments\/vai_pubic_clouds_and_vulnerable_cpus\/slides\/3650\/FOSDEM2020_vkuznets.pdf.  2020. Public clouds and vulnerable CPUs: are we secure?https:\/\/archive.fosdem.org\/2020\/schedule\/event\/vai_pubic_clouds_and_vulnerable_cpus\/attachments\/slides\/3650\/export\/events\/attachments\/vai_pubic_clouds_and_vulnerable_cpus\/slides\/3650\/FOSDEM2020_vkuznets.pdf."},{"key":"e_1_3_2_1_22_1","volume-title":"The 1st Instruction Prefetching Championship. https:\/\/research.ece.ncsu.edu\/ipc\/","unstructured":"2020. The 1st Instruction Prefetching Championship. https:\/\/research.ece.ncsu.edu\/ipc\/ . 2020. The 1st Instruction Prefetching Championship. https:\/\/research.ece.ncsu.edu\/ipc\/."},{"key":"e_1_3_2_1_23_1","unstructured":"2021. AMD64 Architecture Programmer Manual(Volume 2). https:\/\/www.amd.com\/system\/files\/TechDocs\/24593.pdf.  2021. AMD64 Architecture Programmer Manual(Volume 2). https:\/\/www.amd.com\/system\/files\/TechDocs\/24593.pdf."},{"key":"e_1_3_2_1_24_1","unstructured":"2021. Beyond malloc efficiency to fleet efficiency: a hugepage-aware memory allocator. https:\/\/www.usenix.org\/system\/files\/osdi21-hunter.pdf.  2021. Beyond malloc efficiency to fleet efficiency: a hugepage-aware memory allocator. https:\/\/www.usenix.org\/system\/files\/osdi21-hunter.pdf."},{"key":"e_1_3_2_1_25_1","unstructured":"2021. Intel\u00ae 64 and IA-32 Architectures Software Developer Manuals. https:\/\/software.intel.com\/en-us\/articles\/intel-sdm.  2021. Intel\u00ae 64 and IA-32 Architectures Software Developer Manuals. https:\/\/software.intel.com\/en-us\/articles\/intel-sdm."},{"key":"e_1_3_2_1_26_1","unstructured":"Abishek Bhattacharjee. 2010. Inter-core cooperative TLB prefetchers. https:\/\/patents.google.com\/patent\/US8880844B1\/en.  Abishek Bhattacharjee. 2010. Inter-core cooperative TLB prefetchers. https:\/\/patents.google.com\/patent\/US8880844B1\/en."},{"key":"e_1_3_2_1_27_1","volume-title":"Appendix L in \u201dComputer Architecture: A Quantitative Approach","author":"Bhattacharjee Abishek","unstructured":"Abishek Bhattacharjee . 2018. Advanced Concepts on Address Translation , Appendix L in \u201dComputer Architecture: A Quantitative Approach \u201d by Hennessy and Patterson . http:\/\/www.cs.yale.edu\/homes\/abhishek\/abhishek-appendix-l.pdf. Abishek Bhattacharjee. 2018. Advanced Concepts on Address Translation, Appendix L in \u201dComputer Architecture: A Quantitative Approach\u201d by Hennessy and Patterson. http:\/\/www.cs.yale.edu\/homes\/abhishek\/abhishek-appendix-l.pdf."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080209"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/2090181.2090185"},{"key":"e_1_3_2_1_30_1","volume-title":"Memory Hierarchy for Web Search. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA). 643\u2013656","author":"Ayers G.","year":"2018","unstructured":"G. Ayers , J.\u00a0 H. Ahn , C. Kozyrakis , and P. Ranganathan . 2018 . Memory Hierarchy for Web Search. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA). 643\u2013656 . https:\/\/doi.org\/10.1109\/HPCA. 2018 .00061 10.1109\/HPCA.2018.00061 G. Ayers, J.\u00a0H. Ahn, C. Kozyrakis, and P. Ranganathan. 2018. Memory Hierarchy for Web Search. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA). 643\u2013656. https:\/\/doi.org\/10.1109\/HPCA.2018.00061"},{"key":"e_1_3_2_1_31_1","first-page":"5","article-title":"Effective Hardware-Based Data Prefetching for High-Performance Processors","volume":"44","author":"Baer Jean-Loup","year":"1995","unstructured":"Jean-Loup Baer and Tien-Fu Chen . 1995 . Effective Hardware-Based Data Prefetching for High-Performance Processors . IEEE Trans. Comput. 44 , 5 (May 1995), 609\u2013623. https:\/\/doi.org\/10.1109\/12.381947 10.1109\/12.381947 Jean-Loup Baer and Tien-Fu Chen. 1995. Effective Hardware-Based Data Prefetching for High-Performance Processors. IEEE Trans. Comput. 44, 5 (May 1995), 609\u2013623. https:\/\/doi.org\/10.1109\/12.381947","journal-title":"IEEE Trans. Comput."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815970"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000101"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/CSNET.2017.8241986"},{"key":"e_1_3_2_1_35_1","volume-title":"Side Channels in the Cloud: Isolation Challenges, Attacks, and Countermeasures. (March","author":"Bazm Mohammad-Mahdi","year":"2017","unstructured":"Mohammad-Mahdi Bazm , Marc Lacoste , Mario Sudholt , and Jean-Marc Menaud . 2017. Side Channels in the Cloud: Isolation Challenges, Attacks, and Countermeasures. (March 2017 ). https:\/\/hal.inria.fr\/hal-01591808 working paper or preprint. Mohammad-Mahdi Bazm, Marc Lacoste, Mario Sudholt, and Jean-Marc Menaud. 2017. Side Channels in the Cloud: Isolation Challenges, Attacks, and Countermeasures. (March 2017). https:\/\/hal.inria.fr\/hal-01591808 working paper or preprint."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540741"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749717"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736060"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1167473.1167488"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/214451.214455"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037704"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/356571.356573"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/2901318.2901327"},{"key":"e_1_3_2_1_44_1","volume-title":"Using Hugetlbfs for Mapping Application Text Regions. (01","author":"Doshi Kshitij","year":"2006","unstructured":"Kshitij Doshi and Jantz Tran . 2006. Using Hugetlbfs for Mapping Application Text Regions. (01 2006 ). Kshitij Doshi and Jantz Tran. 2006. Using Hugetlbfs for Mapping Application Text Regions. (01 2006)."},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/3330345.3330363"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195686"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.5555\/2643634.2643659"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173194"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240302.3240420"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165128"},{"key":"e_1_3_2_1_52_1","unstructured":"James Wang. 2009. TLB Prefetching. https:\/\/patents.google.com\/patent\/US20110010521.  James Wang. 2009. TLB Prefetching. https:\/\/patents.google.com\/patent\/US20110010521."},{"key":"e_1_3_2_1_53_1","volume-title":"Proceedings of the 29th Annual International Symposium on Computer Architecture(ISCA \u201902)","author":"B.","unstructured":"Gokul\u00a0 B. Kandiraju and Anand Sivasubramaniam. 2002. Going the Distance for TLB Prefetching: An Application-driven Study . In Proceedings of the 29th Annual International Symposium on Computer Architecture(ISCA \u201902) . IEEE Computer Society, Washington, DC, USA, 195\u2013206. http:\/\/dl.acm.org\/citation.cfm?id=545215.545237 Gokul\u00a0B. Kandiraju and Anand Sivasubramaniam. 2002. Going the Distance for TLB Prefetching: An Application-driven Study. In Proceedings of the 29th Annual International Symposium on Computer Architecture(ISCA \u201902). IEEE Computer Society, Washington, DC, USA, 195\u2013206. http:\/\/dl.acm.org\/citation.cfm?id=545215.545237"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750392"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2749471"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446100"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783763"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173178"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.5555\/3026877.3026931"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358294"},{"key":"e_1_3_2_1_61_1","volume-title":"CHiRP: Control-Flow History Reuse Prediction. In 2020 53rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 131\u2013145","author":"Mirbagher-Ajorpaz S.","year":"2020","unstructured":"S. Mirbagher-Ajorpaz , E. Garza , G. Pokam , and D.\u00a0 A. Jim\u00e9nez . 2020 . CHiRP: Control-Flow History Reuse Prediction. In 2020 53rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 131\u2013145 . https:\/\/doi.org\/10.1109\/MICRO50266.2020.00023 10.1109\/MICRO50266.2020.00023 S. Mirbagher-Ajorpaz, E. Garza, G. Pokam, and D.\u00a0A. Jim\u00e9nez. 2020. CHiRP: Control-Flow History Reuse Prediction. In 2020 53rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 131\u2013145. https:\/\/doi.org\/10.1109\/MICRO50266.2020.00023"},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2986212"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165127"},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2017.7863743"},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2019.8661201"},{"key":"e_1_3_2_1_66_1","volume-title":"Jaehyuk Huh. ISCA","author":"Park Chang\u00a0Hyun","year":"2017","unstructured":"Chang\u00a0Hyun Park , Taekyung Heo , Jungi Jeong , and Jaehyuk Huh. ISCA 2017 . Hybrid TLB Coalescing : Improving TLB Translation Coverage Under Diverse Fragmented Memory Allocations. 13. https:\/\/doi.org\/10.1145\/3079856.3080217 10.1145\/3079856.3080217 Chang\u00a0Hyun Park, Taekyung Heo, Jungi Jeong, and Jaehyuk Huh. ISCA 2017. Hybrid TLB Coalescing: Improving TLB Translation Coverage Under Diverse Fragmented Memory Allocations. 13. https:\/\/doi.org\/10.1145\/3079856.3080217"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.5555\/77493"},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835964"},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.32"},{"key":"e_1_3_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830773"},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1145\/3314221.3314637"},{"key":"e_1_3_2_1_72_1","volume-title":"Proceedings of the 32nd Annual ACM\/IEEE International Symposium on Microarchitecture. 16\u201327","author":"Reinman G.","year":"1999","unstructured":"G. Reinman , B. Calder , and T. Austin . 1999. Fetch directed instruction prefetching. In MICRO-32 . Proceedings of the 32nd Annual ACM\/IEEE International Symposium on Microarchitecture. 16\u201327 . https:\/\/doi.org\/10.1109\/MICRO. 1999 .809439 10.1109\/MICRO.1999.809439 G. Reinman, B. Calder, and T. Austin. 1999. Fetch directed instruction prefetching. In MICRO-32. Proceedings of the 32nd Annual ACM\/IEEE International Symposium on Microarchitecture. 16\u201327. https:\/\/doi.org\/10.1109\/MICRO.1999.809439"},{"key":"e_1_3_2_1_73_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080210"},{"key":"e_1_3_2_1_74_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339666"},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1145\/1030083.1030124"},{"key":"e_1_3_2_1_76_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00036"},{"key":"e_1_3_2_1_77_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378493"},{"key":"e_1_3_2_1_78_1","doi-asserted-by":"publisher","DOI":"10.1145\/358923.358939"},{"key":"e_1_3_2_1_79_1","volume-title":"Exploiting Page Table Locality for Agile TLB Prefetching. In 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). 85\u201398","author":"Vavouliotis Georgios","year":"2021","unstructured":"Georgios Vavouliotis , Lluc Alvarez , Vasileios Karakostas , Konstantinos Nikas , Nectarios Koziris , Daniel\u00a0 A. Jim\u00e9nez , and Marc Casas . 2021 . Exploiting Page Table Locality for Agile TLB Prefetching. In 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). 85\u201398 . https:\/\/doi.org\/10.1109\/ISCA52012.2021.00016 10.1109\/ISCA52012.2021.00016 Georgios Vavouliotis, Lluc Alvarez, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris, Daniel\u00a0A. Jim\u00e9nez, and Marc Casas. 2021. Exploiting Page Table Locality for Agile TLB Prefetching. In 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). 85\u201398. https:\/\/doi.org\/10.1109\/ISCA52012.2021.00016"},{"key":"e_1_3_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1145\/2741948.2741964"},{"key":"e_1_3_2_1_81_1","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322223"},{"key":"e_1_3_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1145\/2896377.2901456"},{"key":"e_1_3_2_1_83_1","volume-title":"On the Impact of Instruction Address Translation Overhead. In 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 106\u2013116","author":"Zhou Y.","year":"2019","unstructured":"Y. Zhou , X. Dong , A.\u00a0 L. Cox , and S. Dwarkadas . 2019 . On the Impact of Instruction Address Translation Overhead. In 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 106\u2013116 . https:\/\/doi.org\/10.1109\/ISPASS. 2019 .00018 10.1109\/ISPASS.2019.00018 Y. Zhou, X. Dong, A.\u00a0L. Cox, and S. Dwarkadas. 2019. On the Impact of Instruction Address Translation Overhead. In 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 106\u2013116. https:\/\/doi.org\/10.1109\/ISPASS.2019.00018"}],"event":{"name":"MICRO '21: 54th Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Virtual Event Greece","acronym":"MICRO '21","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["MICRO-54: 54th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3466752.3480049","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3466752.3480049","content-type":"text\/html","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3466752.3480049","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3466752.3480049","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:24:52Z","timestamp":1750195492000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3466752.3480049"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10,17]]},"references-count":83,"alternative-id":["10.1145\/3466752.3480049","10.1145\/3466752"],"URL":"https:\/\/doi.org\/10.1145\/3466752.3480049","relation":{},"subject":[],"published":{"date-parts":[[2021,10,17]]},"assertion":[{"value":"2021-10-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}