{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,21]],"date-time":"2026-07-21T14:27:48Z","timestamp":1784644068892,"version":"3.55.0"},"publisher-location":"New York, NY, USA","reference-count":83,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,10,17]],"date-time":"2021-10-17T00:00:00Z","timestamp":1634428800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2810.022, 2810.021"],"award-info":[{"award-number":["2810.022, 2810.021"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["2106828, 2112562"],"award-info":[{"award-number":["2106828, 2112562"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,10,18]]},"DOI":"10.1145\/3466752.3480064","type":"proceedings-article","created":{"date-parts":[[2021,10,17]],"date-time":"2021-10-17T19:16:55Z","timestamp":1634498215000},"page":"1-14","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":47,"title":["APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors"],"prefix":"10.1145","author":[{"given":"Zhiyao","family":"Xie","sequence":"first","affiliation":[{"name":"Duke University, United States of America"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xiaoqing","family":"Xu","sequence":"additional","affiliation":[{"name":"ARM Ltd."}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Matt","family":"Walker","sequence":"additional","affiliation":[{"name":"ARM Ltd."}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Joshua","family":"Knebel","sequence":"additional","affiliation":[{"name":"ARM Ltd."}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kumaraguru","family":"Palaniswamy","sequence":"additional","affiliation":[{"name":"ARM Ltd."}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nicolas","family":"Hebert","sequence":"additional","affiliation":[{"name":"ARM Ltd."}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiang","family":"Hu","sequence":"additional","affiliation":[{"name":"Texas A&M University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Huanrui","family":"Yang","sequence":"additional","affiliation":[{"name":"Duke University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yiran","family":"Chen","sequence":"additional","affiliation":[{"name":"Duke University, United States of America"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shidhartha","family":"Das","sequence":"additional","affiliation":[{"name":"ARM Ltd., United Kingdom"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2021,10,17]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2021. Ampere Altra SoC. https:\/\/amperecomputing.com\/altra\/.  2021. Ampere Altra SoC. https:\/\/amperecomputing.com\/altra\/."},{"key":"e_1_3_2_1_2_1","unstructured":"2021. Arm Cortex-A77 Core Technical Reference Manual. https:\/\/developer.arm.com\/documentation\/101111\/latest\/preface.  2021. Arm Cortex-A77 Core Technical Reference Manual. https:\/\/developer.arm.com\/documentation\/101111\/latest\/preface."},{"key":"e_1_3_2_1_3_1","unstructured":"2021. Arm Neoverse N1 Core Technical Reference Manual. https:\/\/developer.arm.com\/documentation\/100616\/0301.  2021. Arm Neoverse N1 Core Technical Reference Manual. https:\/\/developer.arm.com\/documentation\/100616\/0301."},{"key":"e_1_3_2_1_4_1","unstructured":"2021. AWS Graviton Processor. https:\/\/aws.amazon.com\/ec2\/graviton\/.  2021. AWS Graviton Processor. https:\/\/aws.amazon.com\/ec2\/graviton\/."},{"key":"e_1_3_2_1_5_1","unstructured":"2021. Catapult\u00ae High-Level Synthesis. https:\/\/www.mentor.com\/hls-lp\/catapult-high-level-synthesis\/.  2021. Catapult\u00ae High-Level Synthesis. https:\/\/www.mentor.com\/hls-lp\/catapult-high-level-synthesis\/."},{"key":"e_1_3_2_1_6_1","unstructured":"2021. Design Compiler\u00ae RTL Synthesis. https:\/\/www.synopsys.com\/implementation-and-signoff\/rtl-synthesis-test\/design-compiler-nxt.html.  2021. Design Compiler\u00ae RTL Synthesis. https:\/\/www.synopsys.com\/implementation-and-signoff\/rtl-synthesis-test\/design-compiler-nxt.html."},{"key":"e_1_3_2_1_7_1","unstructured":"2021. Palladium\u00ae Z1 Enterprise Emulation Platform. https:\/\/www.cadence.com\/enUS\/home\/tools\/system-design-and-verification\/acceleration-and-emulation\/palladium-z1.html.  2021. Palladium\u00ae Z1 Enterprise Emulation Platform. https:\/\/www.cadence.com\/enUS\/home\/tools\/system-design-and-verification\/acceleration-and-emulation\/palladium-z1.html."},{"key":"e_1_3_2_1_8_1","unstructured":"2021. PowerPro\u00ae RTL Low-Power. https:\/\/www.mentor.com\/hls-lp\/powerpro-rtl-low-power\/.  2021. PowerPro\u00ae RTL Low-Power. https:\/\/www.mentor.com\/hls-lp\/powerpro-rtl-low-power\/."},{"key":"e_1_3_2_1_9_1","unstructured":"2021. VCS\u00ae functional verification solution. https:\/\/www.synopsys.com\/verification\/simulation\/vcs.html.  2021. VCS\u00ae functional verification solution. https:\/\/www.synopsys.com\/verification\/simulation\/vcs.html."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/566726.566736"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"crossref","unstructured":"Ramon Bertran Marc Gonzalez Xavier Martorell Nacho Navarro and Eduard Ayguade. 2010. Decomposable and responsive power models for multicore processors using performance counters. In ACM ICS.  Ramon Bertran Marc Gonzalez Xavier Martorell Nacho Navarro and Eduard Ayguade. 2010. Decomposable and responsive power models for multicore processors using performance counters. In ACM ICS.","DOI":"10.1145\/1810085.1810108"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2177129"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"crossref","unstructured":"Srikar Bhagavatula and Byunghoo Jung. 2013. A power sensor with 80ns response time for power management in microprocessors. In CICC.  Srikar Bhagavatula and Byunghoo Jung. 2013. A power sensor with 80ns response time for power management in microprocessors. In CICC.","DOI":"10.1109\/CICC.2013.6658487"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"crossref","unstructured":"Nathan Binkert Bradford Beckmann Gabriel Black Steven\u00a0K Reinhardt Ali Saidi Arkaprava Basu Joel Hestness Derek\u00a0R Hower Tushar Krishna Somayeh Sardashti 2011. The gem5 simulator. ACM SIGARCH computer architecture news(2011).  Nathan Binkert Bradford Beckmann Gabriel Black Steven\u00a0K Reinhardt Ali Saidi Arkaprava Basu Joel Hestness Derek\u00a0R Hower Tushar Krishna Somayeh Sardashti 2011. The gem5 simulator. ACM SIGARCH computer architecture news(2011).","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_15_1","volume-title":"The M5 simulator: Modeling networked systems","author":"Binkert L","year":"2006","unstructured":"Nathan\u00a0 L Binkert , Ronald\u00a0 G Dreslinski , Lisa\u00a0 R Hsu , Kevin\u00a0 T Lim , Ali\u00a0 G Saidi , and Steven\u00a0 K Reinhardt . 2006. The M5 simulator: Modeling networked systems . IEEE Micro ( 2006 ). Nathan\u00a0L Binkert, Ronald\u00a0G Dreslinski, Lisa\u00a0R Hsu, Kevin\u00a0T Lim, Ali\u00a0G Saidi, and Steven\u00a0K Reinhardt. 2006. The M5 simulator: Modeling networked systems. IEEE Micro (2006)."},{"key":"e_1_3_2_1_16_1","volume-title":"Complete system power estimation: A trickle-down approach based on performance events","author":"Bircher W\u00a0Lloyd","unstructured":"W\u00a0Lloyd Bircher and Lizy\u00a0 K John . 2007. Complete system power estimation: A trickle-down approach based on performance events . In IEEE ISPASS. W\u00a0Lloyd Bircher and Lizy\u00a0K John. 2007. Complete system power estimation: A trickle-down approach based on performance events. In IEEE ISPASS."},{"key":"e_1_3_2_1_17_1","volume-title":"Regression-based RTL power modeling. ACM TODAES","author":"Bogliolo Alessandro","year":"2000","unstructured":"Alessandro Bogliolo , Luca Benini , and Giovanni De\u00a0Micheli . 2000. Regression-based RTL power modeling. ACM TODAES ( 2000 ). Alessandro Bogliolo, Luca Benini, and Giovanni De\u00a0Micheli. 2000. Regression-based RTL power modeling. ACM TODAES (2000)."},{"key":"e_1_3_2_1_18_1","volume-title":"A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range","author":"Bowman A","year":"2016","unstructured":"Keith\u00a0 A Bowman , Sarthak Raina , J\u00a0Todd Bridges , Daniel\u00a0 J Yingling , Hoan\u00a0 H Nguyen , Brad\u00a0 R Appel , Yesh\u00a0 N Kolla , Jihoon Jeong , Francois\u00a0 I Atallah , and David\u00a0 W Hansquine . 2016. A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range . IEEE JSSC ( 2016 ). Keith\u00a0A Bowman, Sarthak Raina, J\u00a0Todd Bridges, Daniel\u00a0J Yingling, Hoan\u00a0H Nguyen, Brad\u00a0R Appel, Yesh\u00a0N Kolla, Jihoon Jeong, Francois\u00a0I Atallah, and David\u00a0W Hansquine. 2016. A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range. IEEE JSSC (2016)."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"crossref","unstructured":"David Brooks Pradip Bose Viji Srinivasan Michael\u00a0K Gschwind Philip\u00a0G Emma and Michael\u00a0G Rosenfield. 2003. New methodology for early-stage microarchitecture-level power-performance analysis of microprocessors. IBM Journal of Research and Development(2003).  David Brooks Pradip Bose Viji Srinivasan Michael\u00a0K Gschwind Philip\u00a0G Emma and Michael\u00a0G Rosenfield. 2003. New methodology for early-stage microarchitecture-level power-performance analysis of microprocessors. IBM Journal of Research and Development(2003).","DOI":"10.1147\/rd.475.0653"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"crossref","unstructured":"Robert Christy Stuart Riches Sujil Kottekkat Prasanth Gopinath Ketan Sawant Anitha Kona and Rob Harrison. 2020. A 3GHz ARM Neoverse N1 CPU in 7nm FinFET for Infrastructure Applications. In ISSCC.  Robert Christy Stuart Riches Sujil Kottekkat Prasanth Gopinath Ketan Sawant Anitha Kona and Rob Harrison. 2020. A 3GHz ARM Neoverse N1 CPU in 7nm FinFET for Infrastructure Applications. In ISSCC.","DOI":"10.1109\/ISSCC19947.2020.9062889"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"crossref","unstructured":"Joel Coburn Srivaths Ravi and Anand Raghunathan. 2005. Power emulation: a new paradigm for power estimation. In DAC.  Joel Coburn Srivaths Ravi and Anand Raghunathan. 2005. Power emulation: a new paradigm for power estimation. In DAC.","DOI":"10.1145\/1065579.1065764"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.suscom.2020.100467"},{"key":"e_1_3_2_1_24_1","unstructured":"C Gilberto and M Margaret. 2005. Power prediction for intel xscale processors using performance monitoring unit events. In ISLPED.  C Gilberto and M Margaret. 2005. Power prediction for intel xscale processors using performance monitoring unit events. In ISLPED."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"crossref","unstructured":"Waclaw Godycki Christopher Torng Ivan Bukreyev Alyssa Apsel and Christopher Batten. 2014. Enabling realistic fine-grain voltage scaling with reconfigurable power distribution networks. In MICRO.  Waclaw Godycki Christopher Torng Ivan Bukreyev Alyssa Apsel and Christopher Batten. 2014. Enabling realistic fine-grain voltage scaling with reconfigurable power distribution networks. In MICRO.","DOI":"10.1109\/MICRO.2014.52"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/GREENCOMP.2010.5598313"},{"key":"e_1_3_2_1_27_1","unstructured":"Ed Grochowski David Ayers and Vivek Tiwari. 2002. Microarchitectural simulation and control of di\/dt-induced power supply voltage variation. In HPCA.  Ed Grochowski David Ayers and Vivek Tiwari. 2002. Microarchitectural simulation and control of di\/dt-induced power supply voltage variation. In HPCA."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"crossref","unstructured":"Zacharias Hadjilambrou Shidhartha Das Paul\u00a0N Whatmough David Bull and Yiannakis Sazeides. 2019. GeST: An automatic framework for generating CPU stress-tests. In ISPASS.  Zacharias Hadjilambrou Shidhartha Das Paul\u00a0N Whatmough David Bull and Yiannakis Sazeides. 2019. GeST: An automatic framework for generating CPU stress-tests. In ISPASS.","DOI":"10.1109\/ISPASS.2019.00009"},{"key":"e_1_3_2_1_29_1","volume-title":"Fine-grain power breakdown of modern out-of-order cores and its implications on skylake-based systems. TACO","author":"Haj-Yihia Jawad","year":"2016","unstructured":"Jawad Haj-Yihia , Ahmad Yasin , Yosi\u00a0Ben Asher , and Avi Mendelson . 2016. Fine-grain power breakdown of modern out-of-order cores and its implications on skylake-based systems. TACO ( 2016 ). Jawad Haj-Yihia, Ahmad Yasin, Yosi\u00a0Ben Asher, and Avi Mendelson. 2016. Fine-grain power breakdown of modern out-of-order cores and its implications on skylake-based systems. TACO (2016)."},{"key":"e_1_3_2_1_30_1","volume-title":"Ralf Gommers","author":"Harris R.","year":"2020","unstructured":"Charles\u00a0 R. Harris , K.\u00a0 Jarrod Millman , St\u2019efan\u00a0 J. van\u00a0der Walt , Ralf Gommers , Pauli Virtanen, David Cournapeau , 2020 . Array programming with NumPy. Nature ( 2020). Charles\u00a0R. Harris, K.\u00a0Jarrod Millman, St\u2019efan\u00a0J. van\u00a0der Walt, Ralf Gommers, Pauli Virtanen, David Cournapeau, 2020. Array programming with NumPy. Nature (2020)."},{"key":"e_1_3_2_1_31_1","volume-title":"Ridge regression: applications to nonorthogonal problems. Technometrics","author":"Hoerl E","year":"1970","unstructured":"Arthur\u00a0 E Hoerl and Robert\u00a0 W Kennard . 1970. Ridge regression: applications to nonorthogonal problems. Technometrics ( 1970 ). Arthur\u00a0E Hoerl and Robert\u00a0W Kennard. 1970. Ridge regression: applications to nonorthogonal problems. Technometrics (1970)."},{"key":"e_1_3_2_1_32_1","volume-title":"Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting. In HPCA.","author":"Hsu Chang-Hong","year":"2015","unstructured":"Chang-Hong Hsu , Yunqi Zhang , Michael\u00a0 A Laurenzano , David Meisner , Thomas Wenisch , Jason Mars , Lingjia Tang , and Ronald\u00a0 G Dreslinski . 2015 . Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting. In HPCA. Chang-Hong Hsu, Yunqi Zhang, Michael\u00a0A Laurenzano, David Meisner, Thomas Wenisch, Jason Mars, Lingjia Tang, and Ronald\u00a0G Dreslinski. 2015. Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting. In HPCA."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"crossref","unstructured":"Wei Huang Charles Lefurgy William Kuk Alper Buyuktosunoglu Michael Floyd Karthick Rajamani Malcolm Allen-Ware and Bishop Brock. 2012. Accurate fine-grained processor power proxies. In MICRO.  Wei Huang Charles Lefurgy William Kuk Alper Buyuktosunoglu Michael Floyd Karthick Rajamani Malcolm Allen-Ware and Bishop Brock. 2012. Accurate fine-grained processor power proxies. In MICRO.","DOI":"10.1109\/MICRO.2012.29"},{"key":"e_1_3_2_1_34_1","unstructured":"Canturk Isci and Margaret Martonosi. 2003. Runtime power monitoring in high-end processors: Methodology and empirical data. In MICRO.  Canturk Isci and Margaret Martonosi. 2003. Runtime power monitoring in high-end processors: Methodology and empirical data. In MICRO."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"crossref","unstructured":"Hans Jacobson Alper Buyuktosunoglu Pradip Bose Emrah Acar and Richard Eickemeyer. 2011. Abstraction and microarchitecture scaling in early-stage power modeling. In HPCA.  Hans Jacobson Alper Buyuktosunoglu Pradip Bose Emrah Acar and Richard Eickemeyer. 2011. Abstraction and microarchitecture scaling in early-stage power modeling. In HPCA.","DOI":"10.1109\/HPCA.2011.5749746"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"crossref","unstructured":"R. Joseph and M. Martonosi. 2001. Run-time power estimation in high performance microprocessors. In ISLPED.  R. Joseph and M. Martonosi. 2001. Run-time power estimation in high performance microprocessors. In ISLPED.","DOI":"10.1145\/383082.383119"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"crossref","unstructured":"Vijay\u00a0Kiran Kalyanam Eric Mahurin Keith Bowman and Jacob Abraham. 2020. A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon\u2122 Processor. In VLSI.  Vijay\u00a0Kiran Kalyanam Eric Mahurin Keith Bowman and Jacob Abraham. 2020. A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon\u2122 Processor. In VLSI.","DOI":"10.1109\/VLSICircuits18222.2020.9162808"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"crossref","unstructured":"Vijay\u00a0Kiran Kalyanam Peter\u00a0G Sassone and Jacob\u00a0A Abraham. 2017. Power prediction of embedded scalar and vector processor: Challenges and solutions. In ISQED.  Vijay\u00a0Kiran Kalyanam Peter\u00a0G Sassone and Jacob\u00a0A Abraham. 2017. Power prediction of embedded scalar and vector processor: Challenges and solutions. In ISQED.","DOI":"10.1109\/ISQED.2017.7918320"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830797"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358322"},{"key":"e_1_3_2_1_41_1","volume-title":"Kipf and Max Welling","author":"N.","year":"2017","unstructured":"Thomas\u00a0 N. Kipf and Max Welling . 2017 . Semi-Supervised Classification with Graph Convolutional Networks. In ICLR. Thomas\u00a0N. Kipf and Max Welling. 2017. Semi-Supervised Classification with Graph Convolutional Networks. In ICLR."},{"key":"e_1_3_2_1_42_1","unstructured":"Ajay Krishna\u00a0Ananda Kumar and Andreas Gerstlauer. 2019. Learning-Based CPU Power Modeling. In MLCAD.  Ajay Krishna\u00a0Ananda Kumar and Andreas Gerstlauer. 2019. Learning-Based CPU Power Modeling. In MLCAD."},{"key":"e_1_3_2_1_43_1","unstructured":"Benjamin\u00a0C Lee and David\u00a0M Brooks. 2006. Accurate and efficient regression modeling for microarchitectural performance and power prediction. ACM SIGOPS operating systems review(2006).  Benjamin\u00a0C Lee and David\u00a0M Brooks. 2006. Accurate and efficient regression modeling for microarchitectural performance and power prediction. ACM SIGOPS operating systems review(2006)."},{"key":"e_1_3_2_1_44_1","unstructured":"Dongwook Lee Lizy\u00a0K John and Andreas Gerstlauer. 2015. Dynamic power and performance back-annotation for fast and accurate functional hardware simulation. In DATE.  Dongwook Lee Lizy\u00a0K John and Andreas Gerstlauer. 2015. Dynamic power and performance back-annotation for fast and accurate functional hardware simulation. In DATE."},{"key":"e_1_3_2_1_45_1","unstructured":"Wooseok Lee Youngchun Kim Jee\u00a0Ho Ryoo Dam Sunwoo Andreas Gerstlauer and Lizy\u00a0K John. 2015. PowerTrain: A learning-based calibration of McPAT power models. In ISLPED.  Wooseok Lee Youngchun Kim Jee\u00a0Ho Ryoo Dam Sunwoo Andreas Gerstlauer and Lizy\u00a0K John. 2015. PowerTrain: A learning-based calibration of McPAT power models. In ISLPED."},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"crossref","unstructured":"Joseph Lee\u00a0Rodgers and W\u00a0Alan Nicewander. 1988. Thirteen ways to look at the correlation coefficient. The American Statistician(1988).  Joseph Lee\u00a0Rodgers and W\u00a0Alan Nicewander. 1988. Thirteen ways to look at the correlation coefficient. The American Statistician(1988).","DOI":"10.2307\/2685263"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"crossref","unstructured":"Charles\u00a0R Lefurgy Alan\u00a0J Drake Michael\u00a0S Floyd Malcolm\u00a0S Allen-Ware Bishop Brock Jose\u00a0A Tierno and John\u00a0B Carter. 2011. Active management of timing guardband to save energy in POWER7. In MICRO.  Charles\u00a0R Lefurgy Alan\u00a0J Drake Michael\u00a0S Floyd Malcolm\u00a0S Allen-Ware Bishop Brock Jose\u00a0A Tierno and John\u00a0B Carter. 2011. Active management of timing guardband to save energy in POWER7. In MICRO.","DOI":"10.1145\/2155620.2155622"},{"key":"e_1_3_2_1_48_1","unstructured":"Sheng Li Jung\u00a0Ho Ahn Richard\u00a0D Strong Jay\u00a0B Brockman Dean\u00a0M Tullsen and Norman\u00a0P Jouppi. 2009. McPAT: an integrated power area and timing modeling framework for multicore and manycore architectures. In MICRO.  Sheng Li Jung\u00a0Ho Ahn Richard\u00a0D Strong Jay\u00a0B Brockman Dean\u00a0M Tullsen and Norman\u00a0P Jouppi. 2009. McPAT: an integrated power area and timing modeling framework for multicore and manycore architectures. In MICRO."},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"crossref","unstructured":"Hugh Mair Ericbill Wang Alice Wang Ping Kao Yuwen Tsai Sumanth Gururajarao Rolf Lagerquist Jin Son Gordon Gammie Gordon Lin 2017. 3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance. In ISSCC.  Hugh Mair Ericbill Wang Alice Wang Ping Kao Yuwen Tsai Sumanth Gururajarao Rolf Lagerquist Jin Son Gordon Gammie Gordon Lin 2017. 3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance. In ISSCC.","DOI":"10.1109\/ISSCC.2017.7870258"},{"key":"e_1_3_2_1_50_1","volume-title":"A note on a general definition of the coefficient of determination. Biometrika","author":"JD","year":"1991","unstructured":"Nico\u00a0 JD Nagelkerke 1991. A note on a general definition of the coefficient of determination. Biometrika ( 1991 ). Nico\u00a0JD Nagelkerke 1991. A note on a general definition of the coefficient of determination. Biometrika (1991)."},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2614347"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"crossref","unstructured":"Fabian Oboril Jos Ewert and Mehdi\u00a0B Tahoori. 2015. High-resolution online power monitoring for modern microprocessors. In DATE.  Fabian Oboril Jos Ewert and Mehdi\u00a0B Tahoori. 2015. High-resolution online power monitoring for modern microprocessors. In DATE.","DOI":"10.7873\/DATE.2015.0208"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"crossref","unstructured":"Daniele\u00a0Jahier Pagliari Valentino Peluso Yukai Chen Andrea Calimera Enrico Macii and Massimo Poncino. 2018. All-digital embedded meters for on-line power estimation. In DATE.  Daniele\u00a0Jahier Pagliari Valentino Peluso Yukai Chen Andrea Calimera Enrico Macii and Massimo Poncino. 2018. All-digital embedded meters for on-line power estimation. In DATE.","DOI":"10.23919\/DATE.2018.8342105"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"crossref","unstructured":"Neal Parikh and Stephen Boyd. 2014. Proximal algorithms. Foundations and Trends in optimization(2014).  Neal Parikh and Stephen Boyd. 2014. Proximal algorithms. Foundations and Trends in optimization(2014).","DOI":"10.1561\/9781601987174"},{"key":"e_1_3_2_1_55_1","volume-title":"PyTorch: An Imperative Style","author":"Paszke Adam","year":"2019","unstructured":"Adam Paszke , Sam Gross , Francisco Massa , Adam Lerer , James Bradbury , Gregory Chanan , Trevor Killeen , Zeming Lin , Natalia Gimelshein , Luca Antiga , 2019. PyTorch: An Imperative Style , High-Performance Deep Learning Library . NeurIPs ( 2019 ). Adam Paszke, Sam Gross, Francisco Massa, Adam Lerer, James Bradbury, Gregory Chanan, Trevor Killeen, Zeming Lin, Natalia Gimelshein, Luca Antiga, 2019. PyTorch: An Imperative Style, High-Performance Deep Learning Library. NeurIPs (2019)."},{"key":"e_1_3_2_1_56_1","volume-title":"Scikit-learn: Machine Learning in Python. JMLR","author":"Pedregosa Fabian","year":"2011","unstructured":"Fabian Pedregosa , Ga\u00ebl Varoquaux , Alexandre Gramfort , Vincent Michel , Bertrand Thirion , Olivier Grisel , Mathieu Blondel , Peter Prettenhofer , Ron Weiss , Vincent Dubourg , 2011 . Scikit-learn: Machine Learning in Python. JMLR (2011). Fabian Pedregosa, Ga\u00ebl Varoquaux, Alexandre Gramfort, Vincent Michel, Bertrand Thirion, Olivier Grisel, Mathieu Blondel, Peter Prettenhofer, Ron Weiss, Vincent Dubourg, 2011. Scikit-learn: Machine Learning in Python. JMLR (2011)."},{"key":"e_1_3_2_1_57_1","volume-title":"The Arm Neoverse N1 Platform: Building Blocks for the Next-Gen Cloud-to-Edge Infrastructure SoC","author":"Pellegrini Andrea","year":"2020","unstructured":"Andrea Pellegrini , Nigel Stephens , Magnus Bruce , Yasuo Ishii , Joseph Pusdesris , Abhishek Raja , Chris Abernathy , Jinson Koppanalil , Tushar Ringe , Ashok Tummala , 2020. The Arm Neoverse N1 Platform: Building Blocks for the Next-Gen Cloud-to-Edge Infrastructure SoC . IEEE Micro ( 2020 ). Andrea Pellegrini, Nigel Stephens, Magnus Bruce, Yasuo Ishii, Joseph Pusdesris, Abhishek Raja, Chris Abernathy, Jinson Koppanalil, Tushar Ringe, Ashok Tummala, 2020. The Arm Neoverse N1 Platform: Building Blocks for the Next-Gen Cloud-to-Edge Infrastructure SoC. IEEE Micro (2020)."},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"crossref","unstructured":"Mihai Pricopi Thannirmalai\u00a0Somu Muthukaruppan Vanchinathan Venkataramani Tulika Mitra and Sanjay Vishin. 2013. Power-performance modeling on asymmetric multi-cores. In CASES.  Mihai Pricopi Thannirmalai\u00a0Somu Muthukaruppan Vanchinathan Venkataramani Tulika Mitra and Sanjay Vishin. 2013. Power-performance modeling on asymmetric multi-cores. In CASES.","DOI":"10.1109\/CASES.2013.6662519"},{"key":"e_1_3_2_1_59_1","unstructured":"Vijay\u00a0Janapa Reddi Meeta\u00a0S Gupta Glenn Holloway Gu-Yeon Wei Michael\u00a0D Smith and David Brooks. 2009. Voltage emergency prediction: Using signatures to reduce operating margins. In HPCA.  Vijay\u00a0Janapa Reddi Meeta\u00a0S Gupta Glenn Holloway Gu-Yeon Wei Michael\u00a0D Smith and David Brooks. 2009. Voltage emergency prediction: Using signatures to reduce operating margins. In HPCA."},{"key":"e_1_3_2_1_60_1","volume-title":"Voltage noise in production processors","author":"Reddi Vijay\u00a0Janapa","year":"2010","unstructured":"Vijay\u00a0Janapa Reddi , Svilen Kanev , Wonyoung Kim , Simone Campanoni , Michael\u00a0 D Smith , Gu-Yeon Wei , and David Brooks . 2010. Voltage noise in production processors . IEEE micro ( 2010 ). Vijay\u00a0Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael\u00a0D Smith, Gu-Yeon Wei, and David Brooks. 2010. Voltage noise in production processors. IEEE micro (2010)."},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"crossref","unstructured":"Santhosh\u00a0Kumar Rethinagiri Oscar Palomar Rabie Ben\u00a0Atitallah Smail Niar Osman Unsal and Adrian\u00a0Cristal Kestelman. 2014. System-level power estimation tool for embedded processor based platforms. In RAPIDO.  Santhosh\u00a0Kumar Rethinagiri Oscar Palomar Rabie Ben\u00a0Atitallah Smail Niar Osman Unsal and Adrian\u00a0Cristal Kestelman. 2014. System-level power estimation tool for embedded processor based platforms. In RAPIDO.","DOI":"10.1145\/2555486.2555491"},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2285966"},{"key":"e_1_3_2_1_63_1","volume-title":"Martin Rapp, Thomas Wild, J\u00f6rg Henkel, and Andreas Herkersdorf.","author":"Sagi Mark","year":"2020","unstructured":"Mark Sagi , Nguyen Anh\u00a0Vu Doan , Martin Rapp, Thomas Wild, J\u00f6rg Henkel, and Andreas Herkersdorf. 2020 . A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power. IEEE TCAD ( 2020). Mark Sagi, Nguyen Anh\u00a0Vu Doan, Martin Rapp, Thomas Wild, J\u00f6rg Henkel, and Andreas Herkersdorf. 2020. A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power. IEEE TCAD (2020)."},{"key":"e_1_3_2_1_64_1","volume-title":"Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures. In ISCA.","author":"Shao Yakun\u00a0Sophia","year":"2014","unstructured":"Yakun\u00a0Sophia Shao , Brandon Reagen , Gu-Yeon Wei , and David Brooks . 2014 . Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures. In ISCA. Yakun\u00a0Sophia Shao, Brandon Reagen, Gu-Yeon Wei, and David Brooks. 2014. Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures. In ISCA."},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"crossref","unstructured":"Karan Singh Major Bhadauria and Sally\u00a0A McKee. 2009. Real time power estimation and thread scheduling via performance counters. ACM SIGARCH Computer Architecture News(2009).  Karan Singh Major Bhadauria and Sally\u00a0A McKee. 2009. Real time power estimation and thread scheduling via performance counters. ACM SIGARCH Computer Architecture News(2009).","DOI":"10.1145\/1577129.1577137"},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"crossref","unstructured":"Dam Sunwoo Gene\u00a0Y Wu Nikhil\u00a0A Patil and Derek Chiou. 2010. PrEsto: An FPGA-accelerated power estimation methodology for complex systems. In FPL.  Dam Sunwoo Gene\u00a0Y Wu Nikhil\u00a0A Patil and Derek Chiou. 2010. PrEsto: An FPGA-accelerated power estimation methodology for complex systems. In FPL.","DOI":"10.1109\/FPL.2010.69"},{"key":"e_1_3_2_1_67_1","volume-title":"Regression shrinkage and selection via the lasso. Journal of the Royal Statistical Society: Series B (Methodological)","author":"Tibshirani Robert","year":"1996","unstructured":"Robert Tibshirani . 1996. Regression shrinkage and selection via the lasso. Journal of the Royal Statistical Society: Series B (Methodological) ( 1996 ). Robert Tibshirani. 1996. Regression shrinkage and selection via the lasso. Journal of the Royal Statistical Society: Series B (Methodological) (1996)."},{"key":"e_1_3_2_1_68_1","volume-title":"Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs","author":"Walker J","year":"2016","unstructured":"Matthew\u00a0 J Walker , Stephan Diestelhorst , Andreas Hansson , Anup\u00a0 K Das , Sheng Yang , Bashir\u00a0 M Al-Hashimi , and Geoff\u00a0 V Merrett . 2016. Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs . IEEE TCAD ( 2016 ). Matthew\u00a0J Walker, Stephan Diestelhorst, Andreas Hansson, Anup\u00a0K Das, Sheng Yang, Bashir\u00a0M Al-Hashimi, and Geoff\u00a0V Merrett. 2016. Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs. IEEE TCAD (2016)."},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"crossref","unstructured":"T Webel PM Lobo T Strach PB Parashurama S Purushotham R Bertran and A Buyuktosunoglu. 2020. Proactive power management in IBM z15. IBM Journal of Research and Development(2020).  T Webel PM Lobo T Strach PB Parashurama S Purushotham R Bertran and A Buyuktosunoglu. 2020. Proactive power management in IBM z15. IBM Journal of Research and Development(2020).","DOI":"10.1147\/JRD.2020.3008143"},{"key":"e_1_3_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2018.2880454"},{"key":"e_1_3_2_1_71_1","volume":"201","author":"Stephen\u00a0","unstructured":"Stephen\u00a0 J Wright. 201 5. Coordinate descent algorithms. Mathematical Programming(2015). Stephen\u00a0J Wright. 2015. Coordinate descent algorithms. Mathematical Programming(2015).","journal-title":"J Wright."},{"key":"e_1_3_2_1_72_1","volume-title":"Cycle-accurate macro-models for RT-level power analysis. VLSI","author":"Wu Qing","year":"1998","unstructured":"Qing Wu , Qinru Qiu , Massoud Pedram , and Chih-Shun Ding . 1998. Cycle-accurate macro-models for RT-level power analysis. VLSI ( 1998 ). Qing Wu, Qinru Qiu, Massoud Pedram, and Chih-Shun Ding. 1998. Cycle-accurate macro-models for RT-level power analysis. VLSI (1998)."},{"key":"e_1_3_2_1_73_1","unstructured":"Sam\u00a0Likun Xi Hans Jacobson Pradip Bose Gu-Yeon Wei and David Brooks. 2015. Quantifying sources of error in McPAT and potential impacts on architectural studies. In HPCA.  Sam\u00a0Likun Xi Hans Jacobson Pradip Bose Gu-Yeon Wei and David Brooks. 2015. Quantifying sources of error in McPAT and potential impacts on architectural studies. In HPCA."},{"key":"e_1_3_2_1_74_1","unstructured":"Zhang Xuegong. 2000. Introduction to statistical learning theory and support vector machines. Acta Automatica Sinica(2000).  Zhang Xuegong. 2000. Introduction to statistical learning theory and support vector machines. Acta Automatica Sinica(2000)."},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"crossref","unstructured":"Jianlei Yang Liwei Ma Kang Zhao Yici Cai and Tin-Fook Ngai. 2015. Early stage real-time SoC power estimation using RTL instrumentation. In ASPDAC.  Jianlei Yang Liwei Ma Kang Zhao Yici Cai and Tin-Fook Ngai. 2015. Early stage real-time SoC power estimation using RTL instrumentation. In ASPDAC.","DOI":"10.1109\/ASPDAC.2015.7059105"},{"key":"e_1_3_2_1_76_1","doi-asserted-by":"crossref","unstructured":"Wu Ye Narayanan Vijaykrishnan Mahmut Kandemir and Mary\u00a0Jane Irwin. 2000. The design and use of SimplePower: A cycle-accurate energy estimation tool. In DAC.  Wu Ye Narayanan Vijaykrishnan Mahmut Kandemir and Mary\u00a0Jane Irwin. 2000. The design and use of SimplePower: A cycle-accurate energy estimation tool. In DAC.","DOI":"10.1145\/337292.337436"},{"key":"e_1_3_2_1_77_1","doi-asserted-by":"crossref","unstructured":"Cun-Hui Zhang. 2010. Nearly unbiased variable selection under minimax concave penalty. The Annals of statistics(2010).  Cun-Hui Zhang. 2010. Nearly unbiased variable selection under minimax concave penalty. The Annals of statistics(2010).","DOI":"10.1214\/09-AOS729"},{"key":"e_1_3_2_1_78_1","volume-title":"GRANNITE: Graph Neural Network Inference for Transferable Power Estimation. In DAC.","author":"Zhang Yanqing","year":"2020","unstructured":"Yanqing Zhang , Haoxing Ren , and Brucek Khailany . 2020 . GRANNITE: Graph Neural Network Inference for Transferable Power Estimation. In DAC. Yanqing Zhang, Haoxing Ren, and Brucek Khailany. 2020. GRANNITE: Graph Neural Network Inference for Transferable Power Estimation. In DAC."},{"key":"e_1_3_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317884"},{"key":"e_1_3_2_1_80_1","volume-title":"PowerTap: All-digital power meter modeling for run-time power monitoring","author":"Zoni Davide","year":"2018","unstructured":"Davide Zoni , Luca Cremona , Alessandro Cilardo , Mirko Gagliardi , and William Fornaciari . 2018. PowerTap: All-digital power meter modeling for run-time power monitoring . Elsevier Microprocessors and Microsystems (MICPRO) ( 2018 ). Davide Zoni, Luca Cremona, Alessandro Cilardo, Mirko Gagliardi, and William Fornaciari. 2018. PowerTap: All-digital power meter modeling for run-time power monitoring. Elsevier Microprocessors and Microsystems (MICPRO) (2018)."},{"key":"e_1_3_2_1_81_1","volume-title":"Powerprobe: Run-time power modeling through automatic RTL instrumentation. In DATE.","author":"Zoni Davide","year":"2018","unstructured":"Davide Zoni , Luca Cremona , and William Fornaciari . 2018 . Powerprobe: Run-time power modeling through automatic RTL instrumentation. In DATE. Davide Zoni, Luca Cremona, and William Fornaciari. 2018. Powerprobe: Run-time power modeling through automatic RTL instrumentation. In DATE."},{"key":"e_1_3_2_1_82_1","unstructured":"Yazhou Zu Charles\u00a0R Lefurgy Jingwen Leng Matthew Halpern Michael\u00a0S Floyd and Vijay\u00a0Janapa Reddi. 2015. Adaptive guardband scheduling to improve system-level efficiency of the POWER7+. In MICRO.  Yazhou Zu Charles\u00a0R Lefurgy Jingwen Leng Matthew Halpern Michael\u00a0S Floyd and Vijay\u00a0Janapa Reddi. 2015. Adaptive guardband scheduling to improve system-level efficiency of the POWER7+. In MICRO."},{"key":"e_1_3_2_1_83_1","unstructured":"Yazhou Zu Daniel Richins Charles Lefurgy and Vijay Reddi. 2019. Fine-tuning the active timing margin (ATM) control loop for maximizing multi-core efficiency on an IBM POWER server. In HPCA.  Yazhou Zu Daniel Richins Charles Lefurgy and Vijay Reddi. 2019. Fine-tuning the active timing margin (ATM) control loop for maximizing multi-core efficiency on an IBM POWER server. In HPCA."}],"event":{"name":"MICRO '21: 54th Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Virtual Event Greece","acronym":"MICRO '21","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["MICRO-54: 54th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3466752.3480064","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3466752.3480064","content-type":"text\/html","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3466752.3480064","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3466752.3480064","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:24:53Z","timestamp":1750195493000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3466752.3480064"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10,17]]},"references-count":83,"alternative-id":["10.1145\/3466752.3480064","10.1145\/3466752"],"URL":"https:\/\/doi.org\/10.1145\/3466752.3480064","relation":{},"subject":[],"published":{"date-parts":[[2021,10,17]]},"assertion":[{"value":"2021-10-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}